clkgen.vhd

数字秒表的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clkgen is
generic(fpl:integer:=50000000);
port(clk:in std_logic;
     clk_scan:out std_logic);
end clkgen;
architecture behavioral of clkgen is
signal cnt:integer range 0 to fpl;
begin
process(clk)
begin
if (clk'event and clk='1')then
if(cnt=fpl)then
cnt<=0;
else
cnt<=cnt+1;
end if;
end if;
end process;
process(cnt,clk)
begin
if(clk'event and clk='1')then
if(cnt>=fpl/2)then
clk_scan<='1';
else
clk_scan<='0';
end if;
end if;
end process;
end behavioral;