📄 ddr2_v340_ecc.tan.rpt
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+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+--------------+-----------------------+---------------------+-----------+--------------+
; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ; PLL output ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ; ; PLL output ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.858 ns ; ;
; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk2 ; ; PLL output ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.858 ns ; ;
; clock_source ; ; User Pin ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; ddr2_dqs[3] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[7] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[6] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[0] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[4] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[5] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[8] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[1] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
; ddr2_dqs[2] ; ; User Pin ; 333.33 MHz ; 0.000 ns ; 0.000 ns ; clock_source ; 10 ; 3 ; -3.108 ns ; ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+--------------+-----------------------+---------------------+-----------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0' ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; -0.420 ns ; 292.40 MHz ( period = 3.420 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.821 ns ; 3.241 ns ;
; -0.398 ns ; 294.29 MHz ( period = 3.398 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_4_lfsr_inst|lfsr_data[3] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.822 ns ; 3.220 ns ;
; -0.332 ns ; 300.12 MHz ( period = 3.332 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|time_writes_cas5 ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|accepted ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.826 ns ; 3.158 ns ;
; -0.331 ns ; 300.21 MHz ( period = 3.331 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|time_writes_cas5 ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|accepted~DUPLICATE ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.826 ns ; 3.157 ns ;
; -0.228 ns ; 309.79 MHz ( period = 3.228 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_11_lfsr_inst|lfsr_data[6] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.810 ns ; 3.038 ns ;
; -0.228 ns ; 309.79 MHz ( period = 3.228 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_11_lfsr_inst|lfsr_data[5] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.810 ns ; 3.038 ns ;
; -0.224 ns ; 310.17 MHz ( period = 3.224 ns ) ; ddr2_topecc_example_driver:driver|dgen_enable ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.820 ns ; 3.044 ns ;
; -0.217 ns ; 310.85 MHz ( period = 3.217 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_11_lfsr_inst|lfsr_data[0] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.816 ns ; 3.033 ns ;
; -0.217 ns ; 310.85 MHz ( period = 3.217 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_3_lfsr_inst|lfsr_data[3] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.816 ns ; 3.033 ns ;
; -0.203 ns ; 312.21 MHz ( period = 3.203 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|dqs_toggle_eq_0_regdimm ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|accepted ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.826 ns ; 3.029 ns ;
; -0.202 ns ; 312.30 MHz ( period = 3.202 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|dqs_toggle_eq_0_regdimm ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|accepted~DUPLICATE ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.826 ns ; 3.028 ns ;
; -0.202 ns ; 312.30 MHz ( period = 3.202 ns ) ; ddr2_topecc_example_driver:driver|dgen_enable ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_4_lfsr_inst|lfsr_data[3] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.821 ns ; 3.023 ns ;
; -0.201 ns ; 312.40 MHz ( period = 3.201 ns ) ; ddr2_topecc_example_driver:driver|col_addr[8] ; ddr2_topecc_example_driver:driver|dgen_enable ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.819 ns ; 3.020 ns ;
; -0.199 ns ; 312.60 MHz ( period = 3.199 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_12_lfsr_inst|lfsr_data[0] ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 3.000 ns ; 2.814 ns ; 3.013 ns ;
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