ddr2_v340_ecc.tan.rpt

基于SIIGX的PCIe的Kit

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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                       ; To                                                                                                                                                                                                               ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A       ; None                             ; 6.213 ns                         ; reset_n                                                                                                                                                                                                    ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|time_writes_cas5                                                                       ; --                                                                        ; clock_source                                                              ; 0            ;
; Worst-case tco                                                                           ; N/A       ; None                             ; 5.272 ns                         ; ddr2_topecc_example_driver:driver|compare_valid_reg[10]                                                                                                                                                    ; pnf_per_byte[10]                                                                                                                                                                                                 ; clock_source                                                              ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; 0.194 ns  ; 1.600 ns                         ; 1.406 ns                         ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|dq_captured_falling[0] ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|resynched_data[8]            ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A       ; None                             ; -5.974 ns                        ; reset_n                                                                                                                                                                                                    ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|time_writes_cas5                                                                       ; --                                                                        ; clock_source                                                              ; 0            ;
; Worst-case Maximum Data Arrival Skew                                                     ; 0.090 ns  ; 0.100 ns                         ; 0.010 ns                         ; clk_to_sdram_p[0]                                                                                                                                                                                          ; clk_to_sdram_n[0]                                                                                                                                                                                                ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0' ; -0.420 ns ; 333.33 MHz ( period = 3.000 ns ) ; 292.40 MHz ( period = 3.420 ns ) ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid                                                                ; ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]                                                                                                                                 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 77           ;
; Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1' ; 0.381 ns  ; 333.33 MHz ( period = 3.000 ns ) ; N/A                              ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7]             ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'  ; 0.018 ns  ; 333.33 MHz ( period = 3.000 ns ) ; N/A                              ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|trfc_pipe[23]                                                                    ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|trfc_pipe[24]                                                                          ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'  ; 1.105 ns  ; 333.33 MHz ( period = 3.000 ns ) ; N/A                              ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|doing_rd_delayed       ; ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|dq_enable_reset[0]           ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ; ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ; 0            ;
; Total number of failed paths                                                             ;           ;                                  ;                                  ;                                                                                                                                                                                                            ;                                                                                                                                                                                                                  ;                                                                           ;                                                                           ; 77           ;
+------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                                                                         ;
+-------------------------------------------------------+--------------------+---------------------------------------------------------------------------+---------------------------+-------------+
; Option                                                ; Setting            ; From                                                                      ; To                        ; Entity Name ;
+-------------------------------------------------------+--------------------+---------------------------------------------------------------------------+---------------------------+-------------+
; Device Name                                           ; EP2SGX90FF1508C3   ;                                                                           ;                           ;             ;
; Timing Models                                         ; Final              ;                                                                           ;                           ;             ;