ddr2_v340_ecc.tan.rpt

基于SIIGX的PCIe的Kit

Classic Timing Analyzer report for ddr2_v340_ecc
Thu Aug 02 13:09:45 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'
  6. Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'
  7. Clock Hold: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'
  8. Clock Hold: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. DQS (Read strobe to core register delays)
 14. DQS Delay Chain Timings
 15. Maximum Data Arrival Skew
 16. Timing Analyzer INI Usage
 17. Timing Analyzer Messages



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; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any