ddr2_v340_ecc.fit.qmsg

基于SIIGX的PCIe的Kit

{ "Info" "IFSAC_FSAC_PLACED_DLL_DUE_TO_LOCATION_CONSTRAINTS" "ddr2_topecc_auk_ddr_dll:dll\|dll DLL_X56_Y0_N0 " "Info: Placed DLL \"ddr2_topecc_auk_ddr_dll:dll\|dll\" in location DLL_X56_Y0_N0 due to location constraints" { { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[0\] AT9 User Location Constraints " "Info: I/O \"ddr2_dqs\[0\]\" of type DQS has location assignment AT9 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[0\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[0] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[0\] AU9 User Location Constraints " "Info: I/O \"ddr2_dq\[0\]\" of type DQ has location assignment AU9 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[0\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[0] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[1\] AN10 User Location Constraints " "Info: I/O \"ddr2_dq\[1\]\" of type DQ has location assignment AN10 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[1\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[1] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[2\] AP10 User Location Constraints " "Info: I/O \"ddr2_dq\[2\]\" of type DQ has location assignment AP10 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[2\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[2] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[3\] AW9 User Location Constraints " "Info: I/O \"ddr2_dq\[3\]\" of type DQ has location assignment AW9 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[3\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[3] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[4\] AV10 User Location Constraints " "Info: I/O \"ddr2_dq\[4\]\" of type DQ has location assignment AV10 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[4\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[4] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[5\] AU10 User Location Constraints " "Info: I/O \"ddr2_dq\[5\]\" of type DQ has location assignment AU10 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[5\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[5] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[6\] AN11 User Location Constraints " "Info: I/O \"ddr2_dq\[6\]\" of type DQ has location assignment AN11 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[6\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[6] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[7\] AW10 User Location Constraints " "Info: I/O \"ddr2_dq\[7\]\" of type DQ has location assignment AW10 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[7\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[7] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[1\] AU12 User Location Constraints " "Info: I/O \"ddr2_dqs\[1\]\" of type DQS has location assignment AU12 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[1\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[1] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[8\] AT12 User Location Constraints " "Info: I/O \"ddr2_dq\[8\]\" of type DQ has location assignment AT12 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[8\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[8] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[8] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[9\] AW11 User Location Constraints " "Info: I/O \"ddr2_dq\[9\]\" of type DQ has location assignment AW11 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[9\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[9] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[9] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[10\] AR12 User Location Constraints " "Info: I/O \"ddr2_dq\[10\]\" of type DQ has location assignment AR12 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[10\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[10] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[10] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[11\] AW12 User Location Constraints " "Info: I/O \"ddr2_dq\[11\]\" of type DQ has location assignment AW12 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[11\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[11] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[11] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[12\] AN13 User Location Constraints " "Info: I/O \"ddr2_dq\[12\]\" of type DQ has location assignment AN13 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[12\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[12] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[12] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[13\] AT13 User Location Constraints " "Info: I/O \"ddr2_dq\[13\]\" of type DQ has location assignment AT13 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[13\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[13] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[13] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[14\] AN12 User Location Constraints " "Info: I/O \"ddr2_dq\[14\]\" of type DQ has location assignment AN12 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[14\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[14] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[14] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[15\] AU13 User Location Constraints " "Info: I/O \"ddr2_dq\[15\]\" of type DQ has location assignment AU13 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[15\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[15] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[15] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[2\] AT14 User Location Constraints " "Info: I/O \"ddr2_dqs\[2\]\" of type DQS has location assignment AT14 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[2\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[2] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[16\] AW13 User Location Constraints " "Info: I/O \"ddr2_dq\[16\]\" of type DQ has location assignment AW13 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[16\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[16] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[16] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[17\] AN14 User Location Constraints " "Info: I/O \"ddr2_dq\[17\]\" of type DQ has location assignment AN14 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[17\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[17] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[17] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[18\] AV13 User Location Constraints " "Info: I/O \"ddr2_dq\[18\]\" of type DQ has location assignment AV13 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[18\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[18] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[19\] AP14 User Location Constraints " "Info: I/O \"ddr2_dq\[19\]\" of type DQ has location assignment AP14 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[19\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[19] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[19] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[20\] AT15 User Location Constraints " "Info: I/O \"ddr2_dq\[20\]\" of type DQ has location assignment AT15 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[20\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[20] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[20] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[21\] AR15 User Location Constraints " "Info: I/O \"ddr2_dq\[21\]\" of type DQ has location assignment AR15 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[21\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[21] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[21] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[22\] AW14 User Location Constraints " "Info: I/O \"ddr2_dq\[22\]\" of type DQ has location assignment AW14 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[22\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[22] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[22] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[23\] AW15 User Location Constraints " "Info: I/O \"ddr2_dq\[23\]\" of type DQ has location assignment AW15 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[23\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[23] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[23] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[3\] AP15 User Location Constraints " "Info: I/O \"ddr2_dqs\[3\]\" of type DQS has location assignment AP15 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[3\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[3] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[24\] AN16 User Location Constraints " "Info: I/O \"ddr2_dq\[24\]\" of type DQ has location assignment AN16 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[24\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[24] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[24] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[25\] AN15 User Location Constraints " "Info: I/O \"ddr2_dq\[25\]\" of type DQ has location assignment AN15 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[25\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[25] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[25] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[26\] AU16 User Location Constraints " "Info: I/O \"ddr2_dq\[26\]\" of type DQ has location assignment AU16 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[26\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[26] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[26] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[27\] AT16 User Location Constraints " "Info: I/O \"ddr2_dq\[27\]\" of type DQ has location assignment AT16 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[27\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[27] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[27] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[28\] AN17 User Location Constraints " "Info: I/O \"ddr2_dq\[28\]\" of type DQ has location assignment AN17 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[28\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[28] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[28] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[29\] AW16 User Location Constraints " "Info: I/O \"ddr2_dq\[29\]\" of type DQ has location assignment AW16 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[29\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[29] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[30\] AV16 User Location Constraints " "Info: I/O \"ddr2_dq\[30\]\" of type DQ has location assignment AV16 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[30\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[30] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[30] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[31\] AP17 User Location Constraints " "Info: I/O \"ddr2_dq\[31\]\" of type DQ has location assignment AP17 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[31\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[31] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[4\] AV18 User Location Constraints " "Info: I/O \"ddr2_dqs\[4\]\" of type DQS has location assignment AV18 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[4\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[4] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[32\] AW18 User Location Constraints " "Info: I/O \"ddr2_dq\[32\]\" of type DQ has location assignment AW18 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[32\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[32] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[32] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[33\] AT18 User Location Constraints " "Info: I/O \"ddr2_dq\[33\]\" of type DQ has location assignment AT18 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[33\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[33] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[33] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[34\] AW17 User Location Constraints " "Info: I/O \"ddr2_dq\[34\]\" of type DQ has location assignment AW17 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[34\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[34] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[34] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[35\] AR18 User Location Constraints " "Info: I/O \"ddr2_dq\[35\]\" of type DQ has location assignment AR18 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[35\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[35] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[35] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[36\] AN18 User Location Constraints " "Info: I/O \"ddr2_dq\[36\]\" of type DQ has location assignment AN18 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[36\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[36] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[36] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[37\] AT19 User Location Constraints " "Info: I/O \"ddr2_dq\[37\]\" of type DQ has location assignment AT19 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[37\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[37] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[37] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[38\] AU19 User Location Constraints " "Info: I/O \"ddr2_dq\[38\]\" of type DQ has location assignment AU19 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[38\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[38] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[38] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[39\] AN19 User Location Constraints " "Info: I/O \"ddr2_dq\[39\]\" of type DQ has location assignment AN19 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[39\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[39] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[39] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[5\] AU23 User Location Constraints " "Info: I/O \"ddr2_dqs\[5\]\" of type DQS has location assignment AU23 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[5\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[5] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[40\] AP23 User Location Constraints " "Info: I/O \"ddr2_dq\[40\]\" of type DQ has location assignment AP23 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[40\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[40] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[40] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[41\] AW23 User Location Constraints " "Info: I/O \"ddr2_dq\[41\]\" of type DQ has location assignment AW23 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[41\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[41] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[41] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[42\] AW24 User Location Constraints " "Info: I/O \"ddr2_dq\[42\]\" of type DQ has location assignment AW24 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[42\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[42] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[42] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[43\] AV24 User Location Constraints " "Info: I/O \"ddr2_dq\[43\]\" of type DQ has location assignment AV24 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[43\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[43] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[43] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[44\] AT24 User Location Constraints " "Info: I/O \"ddr2_dq\[44\]\" of type DQ has location assignment AT24 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[44\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[44] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[44] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[45\] AP24 User Location Constraints " "Info: I/O \"ddr2_dq\[45\]\" of type DQ has location assignment AP24 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[45\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[45] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[45] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[46\] AW25 User Location Constraints " "Info: I/O \"ddr2_dq\[46\]\" of type DQ has location assignment AW25 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[46\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[46] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[46] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[47\] AV25 User Location Constraints " "Info: I/O \"ddr2_dq\[47\]\" of type DQ has location assignment AV25 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[47\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[47] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[47] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[6\] AT25 User Location Constraints " "Info: I/O \"ddr2_dqs\[6\]\" of type DQS has location assignment AT25 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[6\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[6] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[48\] AP25 User Location Constraints " "Info: I/O \"ddr2_dq\[48\]\" of type DQ has location assignment AP25 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[48\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[48] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[48] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[49\] AR25 User Location Constraints " "Info: I/O \"ddr2_dq\[49\]\" of type DQ has location assignment AR25 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[49\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[49] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[49] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[50\] AU26 User Location Constraints " "Info: I/O \"ddr2_dq\[50\]\" of type DQ has location assignment AU26 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[50\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[50] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[50] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[51\] AW26 User Location Constraints " "Info: I/O \"ddr2_dq\[51\]\" of type DQ has location assignment AW26 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[51\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[51] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[51] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[52\] AU27 User Location Constraints " "Info: I/O \"ddr2_dq\[52\]\" of type DQ has location assignment AU27 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[52\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[52] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[52] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[53\] AW27 User Location Constraints " "Info: I/O \"ddr2_dq\[53\]\" of type DQ has location assignment AW27 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[53\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[53] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[53] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[54\] AW28 User Location Constraints " "Info: I/O \"ddr2_dq\[54\]\" of type DQ has location assignment AW28 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[54\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[54] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[54] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[55\] AT27 User Location Constraints " "Info: I/O \"ddr2_dq\[55\]\" of type DQ has location assignment AT27 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[55\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[55] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[55] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[7\] AU28 User Location Constraints " "Info: I/O \"ddr2_dqs\[7\]\" of type DQS has location assignment AU28 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[7\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[7] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[56\] AT28 User Location Constraints " "Info: I/O \"ddr2_dq\[56\]\" of type DQ has location assignment AT28 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[56\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[56] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[56] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[57\] AW29 User Location Constraints " "Info: I/O \"ddr2_dq\[57\]\" of type DQ has location assignment AW29 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[57\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[57] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[57] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[58\] AR28 User Location Constraints " "Info: I/O \"ddr2_dq\[58\]\" of type DQ has location assignment AR28 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[58\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[58] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[58] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[59\] AT29 User Location Constraints " "Info: I/O \"ddr2_dq\[59\]\" of type DQ has location assignment AT29 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[59\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[59] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[59] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[60\] AU30 User Location Constraints " "Info: I/O \"ddr2_dq\[60\]\" of type DQ has location assignment AU30 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[60\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[60] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[60] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[61\] AW30 User Location Constraints " "Info: I/O \"ddr2_dq\[61\]\" of type DQ has location assignment AW30 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[61\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[61] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[61] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[62\] AW31 User Location Constraints " "Info: I/O \"ddr2_dq\[62\]\" of type DQ has location assignment AW31 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[62\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[62] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[62] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[63\] AU31 User Location Constraints " "Info: I/O \"ddr2_dq\[63\]\" of type DQ has location assignment AU31 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[63\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[63] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[63] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQS ddr2_dqs\[8\] AW33 User Location Constraints " "Info: I/O \"ddr2_dqs\[8\]\" of type DQS has location assignment AW33 due to source User Location Constraints" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dqs\[8\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[8] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dqs[8] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[64\] AW32 User Location Constraints " "Info: I/O \"ddr2_dq\[64\]\" of type DQ has location assignment AW32 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[64\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[64] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[64] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[65\] AU32 User Location Constraints " "Info: I/O \"ddr2_dq\[65\]\" of type DQ has location assignment AU32 due to source User Location Constraints" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_dq\[65\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[65] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_dq[65] } "NODE_NAME" } }  } 0 0 "I/O \"%2!s!\" of type %1!s! has location assignment %3!s! due to source %4!s!" 0 0} { "Info" "IFSAC_FSAC_IO_CELL_HAS_LOCATION_CONSTRAINT" "DQ ddr2_dq\[66\] AU33 User Location Constraints " "Info: I/O \"ddr2_dq\[66\]\" of type DQ has location assignment AU33 due to source