ddr2_v340_ecc.fit.qmsg

来自「基于SIIGX的PCIe的Kit」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_DQS_HAS_NUMBER_OF_ELEMENTS" "9 DQS I/Os " "Info: Design contains 9 DQS I/Os" {  } {  } 0 0 "Design contains %1!d! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_DQS_HAS_NUMBER_OF_ELEMENTS" "72 DQ I/Os " "Info: Design contains 72 DQ I/Os" {  } {  } 0 0 "Design contains %1!d! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_DLL_LOCK_NUM_FAST_LOCK" "ddr2_topecc_auk_ddr_dll:dll\|dll 256 " "Info: DLL \"ddr2_topecc_auk_ddr_dll:dll\|dll\" (in fast lock mode) requires up to 256 clock cycles to generate correct delay control settings on system power-up" {  } { { "ddr2_topecc_auk_ddr_dll.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dll.v" 59 -1 0 } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_topecc_auk_ddr_dll:dll|dll~UPNDNOUT } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_topecc_auk_ddr_dll:dll|dll~UPNDNOUT } "NODE_NAME" } }  } 0 0 "DLL \"%1!s!\" (in fast lock mode) requires up to %2!d! clock cycles to generate correct delay control settings on system power-up" 0 0}