ddr2_v340_ecc.map.qmsg

基于SIIGX的PCIe的Kit

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_ddr2_init ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|auk_ddr2_init:\\g_ddr2_init:init_block " "Info: Elaborating entity \"auk_ddr2_init\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|auk_ddr2_init:\\g_ddr2_init:init_block\"" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" "\\g_ddr2_init:init_block" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" 2233 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_ddr_timers ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|auk_ddr_timers:\\g_timers:0:bank_timer " "Info: Elaborating entity \"auk_ddr_timers\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|auk_ddr_timers:\\g_timers:0:bank_timer\"" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" "\\g_timers:0:bank_timer" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" 3269 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ddr2_topecc_auk_ddr_datapath.v 1 1 " "Warning: Using design file ddr2_topecc_auk_ddr_datapath.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_topecc_auk_ddr_datapath " "Info: Found entity 1: ddr2_topecc_auk_ddr_datapath" {  } { { "ddr2_topecc_auk_ddr_datapath.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_datapath.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr2_topecc_auk_ddr_datapath ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io " "Info: Elaborating entity \"ddr2_topecc_auk_ddr_datapath\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\"" {  } { { "ddr2_topecc_auk_ddr_sdram.v" "ddr_io" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_sdram.v" 307 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ddr2_topecc_auk_ddr_clk_gen.v 1 1 " "Warning: Using design file ddr2_topecc_auk_ddr_clk_gen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_topecc_auk_ddr_clk_gen " "Info: Found entity 1: ddr2_topecc_auk_ddr_clk_gen" {  } { { "ddr2_topecc_auk_ddr_clk_gen.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_clk_gen.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr2_topecc_auk_ddr_clk_gen ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen " "Info: Elaborating entity \"ddr2_topecc_auk_ddr_clk_gen\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\"" {  } { { "ddr2_topecc_auk_ddr_datapath.v" "ddr_clk_gen" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_datapath.v" 96 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/altddio_out.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/altddio_out.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altddio_out " "Info: Found entity 1: altddio_out" {  } { { "altddio_out.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altddio_out.tdf" 84 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\|altddio_out:ddr_clk_out_p " "Info: Elaborating entity \"altddio_out\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\|altddio_out:ddr_clk_out_p\"" {  } { { "ddr2_topecc_auk_ddr_clk_gen.v" "ddr_clk_out_p" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_clk_gen.v" 66 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\|altddio_out:ddr_clk_out_p " "Info: Elaborated megafunction instantiation \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\|altddio_out:ddr_clk_out_p\"" {  } { { "ddr2_topecc_auk_ddr_clk_gen.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_clk_gen.v" 66 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_t6f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/ddio_out_t6f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_t6f " "Info: Found entity 1: ddio_out_t6f" {  } { { "db/ddio_out_t6f.tdf" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/ddio_out_t6f.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_t6f ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\|altddio_out:ddr_clk_out_p\|ddio_out_t6f:auto_generated " "Info: Elaborating entity \"ddio_out_t6f\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen\|altddio_out:ddr_clk_out_p\|ddio_out_t6f:auto_generated\"" {  } { { "altddio_out.tdf" "auto_generated" { Text "d:/altera/70/quartus/libraries/megafunctions/altddio_out.tdf" 104 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ddr2_topecc_auk_ddr_dqs_group.v 1 1 " "Warning: Using design file ddr2_topecc_auk_ddr_dqs_group.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_topecc_auk_ddr_dqs_group " "Info: Found entity 1: ddr2_topecc_auk_ddr_dqs_group" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr2_topecc_auk_ddr_dqs_group ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io " "Info: Elaborating entity \"ddr2_topecc_auk_ddr_dqs_group\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\"" {  } { { "ddr2_topecc_auk_ddr_datapath.v" "\\g_datapath:0:g_ddr_io" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_datapath.v" 126 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|altddio_out:dm_pin " "Info: Elaborating entity \"altddio_out\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|altddio_out:dm_pin\"" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "dm_pin" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 186 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|altddio_out:dm_pin " "Info: Elaborated megafunction instantiation \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|altddio_out:dm_pin\"" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 186 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_tkf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/ddio_out_tkf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_tkf " "Info: Found entity 1: ddio_out_tkf" {  } { { "db/ddio_out_tkf.tdf" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/ddio_out_tkf.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_tkf ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|altddio_out:dm_pin\|ddio_out_tkf:auto_generated " "Info: Elaborating entity \"ddio_out_tkf\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|altddio_out:dm_pin\|ddio_out_tkf:auto_generated\"" {  } { { "altddio_out.tdf" "auto_generated" { Text "d:/altera/70/quartus/libraries/megafunctions/altddio_out.tdf" 104 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ddr2_topecc_example_driver.v 1 1 " "Warning: Using design file ddr2_topecc_example_driver.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_topecc_example_driver " "Info: Found entity 1: ddr2_topecc_example_driver" {  } { { "ddr2_topecc_example_driver.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr2_topecc_example_driver ddr2_topecc_example_driver:driver " "Info: Elaborating entity \"ddr2_topecc_example_driver\" for hierarchy \"ddr2_topecc_example_driver:driver\"" {  } { { "ddr2_v340_ecc.v" "driver" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_v340_ecc.v" 240 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v 1 1 " "Warning: Using design file E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 example_lfsr8 " "Info: Found entity 1: example_lfsr8" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}