ddr2_v340_ecc.map.qmsg

来自「基于SIIGX的PCIe的Kit」· QMSG 代码 · 共 97 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_0_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 166 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(28) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(28): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_1_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_1_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_1_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 182 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(28) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(28): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_2_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_2_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_2_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 198 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(28) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(28): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_3_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_3_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_3_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 214 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(28) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(28): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_4_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_4_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_4_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 230 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(28) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(28): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_5_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_5_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_5_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 246 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(28) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(28): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "example_lfsr8 ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_6_lfsr_inst " "Info: Elaborating entity \"example_lfsr8\" for hierarchy \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_6_lfsr_inst\"" {  } { { "ddr2_topecc_example_driver.v" "LFSRGEN_6_lfsr_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v" 262 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 example_lfsr8.v(22) " "Warning (10230): Verilog HDL assignment warning at example_lfsr8.v(22): truncated value with size 32 to match size of target (8)" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}