ddr2_v340_ecc.map.qmsg

基于SIIGX的PCIe的Kit

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 02 12:57:45 2007 " "Info: Processing started: Thu Aug 02 12:57:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ddr2_v340_ecc -c ddr2_v340_ecc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ddr2_v340_ecc -c ddr2_v340_ecc" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_ddr_tb_functions " "Info: Found design unit 1: auk_ddr_tb_functions" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd" 23 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_ddr_tb_functions-body " "Info: Found design unit 2: auk_ddr_tb_functions-body" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WCPT_DEFAULTING_TO_OPENCORE" "DDR SDRAM Controller (6AF7_00A8) " "Warning: Defaulting to OpenCore or OpenCore Plus compilation for core DDR SDRAM Controller (6AF7_00A8)" {  } {  } 0 0 "Defaulting to OpenCore or OpenCore Plus compilation for core %1!s!" 0 0}
{ "Warning" "WCPT_PRELIMINARY_FAMILY_SUPPORT" "DDR SDRAM Controller (6AF7_00A8) Stratix II GX " "Warning: Support for IP core DDR SDRAM Controller (6AF7_00A8) in device family Stratix II GX is preliminary and specifications are subject to change" {  } {  } 0 0 "Support for IP core %1!s! in device family %2!s! is preliminary and specifications are subject to change" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_ddr_functions " "Info: Found design unit 1: auk_ddr_functions" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd" 5 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_ddr_functions-body " "Info: Found design unit 2: auk_ddr_functions-body" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 custom_fifo-rtl " "Info: Found design unit 1: custom_fifo-rtl" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_ddr_input_buf-rtl " "Info: Found design unit 2: auk_ddr_input_buf-rtl" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" 264 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 custom_fifo " "Info: Found entity 1: custom_fifo" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 auk_ddr_input_buf " "Info: Found entity 2: auk_ddr_input_buf" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd" 221 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_ddr_timers-rtl " "Info: Found design unit 1: auk_ddr_timers-rtl" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_ddr_timers " "Info: Found entity 1: auk_ddr_timers" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_ddr_avalon_if-rtl " "Info: Found design unit 1: auk_ddr_avalon_if-rtl" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd" 75 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_ddr_avalon_if " "Info: Found entity 1: auk_ddr_avalon_if" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_ddr_bank_details-rtl " "Info: Found design unit 1: auk_ddr_bank_details-rtl" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_ddr_bank_details " "Info: Found entity 1: auk_ddr_bank_details" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WCPT_DEFAULTING_TO_OPENCORE" "DDR2 SDRAM Controller (6AF7_00A7) " "Warning: Defaulting to OpenCore or OpenCore Plus compilation for core DDR2 SDRAM Controller (6AF7_00A7)" {  } {  } 0 0 "Defaulting to OpenCore or OpenCore Plus compilation for core %1!s!" 0 0}
{ "Warning" "WCPT_PRELIMINARY_FAMILY_SUPPORT" "DDR2 SDRAM Controller (6AF7_00A7) Stratix II GX " "Warning: Support for IP core DDR2 SDRAM Controller (6AF7_00A7) in device family Stratix II GX is preliminary and specifications are subject to change" {  } {  } 0 0 "Support for IP core %1!s! in device family %2!s! is preliminary and specifications are subject to change" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_ddr2_init-rtl " "Info: Found design unit 1: auk_ddr2_init-rtl" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd" 84 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_ddr2_init " "Info: Found entity 1: auk_ddr2_init" {  } { { "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr2_topecc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ddr2_topecc.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_topecc " "Info: Found entity 1: ddr2_topecc" {  } { { "ddr2_topecc.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc.v" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ddr2_v340_ecc.v 1 1 " "Warning: Using design file ddr2_v340_ecc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_v340_ecc " "Info: Found entity 1: ddr2_v340_ecc" {  } { { "ddr2_v340_ecc.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_v340_ecc.v" 67 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ddr2_v340_ecc " "Info: Elaborating entity \"ddr2_v340_ecc\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr2_topecc ddr2_topecc:ddr2_topecc_ddr_sdram " "Info: Elaborating entity \"ddr2_topecc\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\"" {  } { { "ddr2_v340_ecc.v" "ddr2_topecc_ddr_sdram" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_v340_ecc.v" 207 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ddr2_topecc_auk_ddr_sdram.v 1 1 " "Warning: Using design file ddr2_topecc_auk_ddr_sdram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ddr2_topecc_auk_ddr_sdram " "Info: Found entity 1: ddr2_topecc_auk_ddr_sdram" {  } { { "ddr2_topecc_auk_ddr_sdram.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_sdram.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr2_topecc_auk_ddr_sdram ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst " "Info: Elaborating entity \"ddr2_topecc_auk_ddr_sdram\" for hierarchy \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\"" {  } { { "ddr2_topecc.v" "ddr2_topecc_auk_ddr_sdram_inst" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc.v" 179 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}