fir.csf.qmsg

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sub131314.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file sub131314.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sub131314-a " "Info: Found design unit 1: sub131314-a" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub131314.vhd" "sub131314-a" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub131314.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sub131314 " "Info: Found entity 1: sub131314" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub131314.vhd" "sub131314" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub131314.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sub141616.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file sub141616.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sub141616-a " "Info: Found design unit 1: sub141616-a" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub141616.vhd" "sub141616-a" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub141616.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sub141616 " "Info: Found entity 1: sub141616" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub141616.vhd" "sub141616" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/sub141616.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir.bdf 1 1 " "Info: Found 1 design units and 1 entities in source file fir.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fir " "Info: Found entity 1: fir" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "fir" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult12.vhd(23) " "Warning: VHDL Process Statement warning at mult12.vhd(23): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult12.vhd(23) " "Warning: VHDL Process Statement warning at mult12.vhd(23): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult12.vhd(26) " "Warning: VHDL Process Statement warning at mult12.vhd(26): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult12.vhd(26) " "Warning: VHDL Process Statement warning at mult12.vhd(26): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult18.vhd(24) " "Warning: VHDL Process Statement warning at mult18.vhd(24): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult18.vhd(24) " "Warning: VHDL Process Statement warning at mult18.vhd(24): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult18.vhd(27) " "Warning: VHDL Process Statement warning at mult18.vhd(27): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult18.vhd(27) " "Warning: VHDL Process Statement warning at mult18.vhd(27): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult18.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult13.vhd(24) " "Warning: VHDL Process Statement warning at mult13.vhd(24): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult13.vhd(24) " "Warning: VHDL Process Statement warning at mult13.vhd(24): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult13.vhd(27) " "Warning: VHDL Process Statement warning at mult13.vhd(27): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult13.vhd(27) " "Warning: VHDL Process Statement warning at mult13.vhd(27): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult13.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult29.vhd(27) " "Warning: VHDL Process Statement warning at mult29.vhd(27): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult29.vhd(27) " "Warning: VHDL Process Statement warning at mult29.vhd(27): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult29.vhd(27) " "Warning: VHDL Process Statement warning at mult29.vhd(27): signal s3 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult29.vhd(30) " "Warning: VHDL Process Statement warning at mult29.vhd(30): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult29.vhd(30) " "Warning: VHDL Process Statement warning at mult29.vhd(30): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult29.vhd" 30 0 0 } }  } 0}