fir.map.qmsg

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult14.vhd(29) " "Warning: VHDL Process Statement warning at mult14.vhd(29): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult14.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult14.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult14.vhd(29) " "Warning: VHDL Process Statement warning at mult14.vhd(29): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult14.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult14.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult14.vhd(29) " "Warning: VHDL Process Statement warning at mult14.vhd(29): signal s3 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult14.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult14.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult162.vhd(27) " "Warning: VHDL Process Statement warning at mult162.vhd(27): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult162.vhd(27) " "Warning: VHDL Process Statement warning at mult162.vhd(27): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult162.vhd(27) " "Warning: VHDL Process Statement warning at mult162.vhd(27): signal s3 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult162.vhd(30) " "Warning: VHDL Process Statement warning at mult162.vhd(30): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult162.vhd(30) " "Warning: VHDL Process Statement warning at mult162.vhd(30): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult162.vhd(30) " "Warning: VHDL Process Statement warning at mult162.vhd(30): signal s3 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult242.vhd(29) " "Warning: VHDL Process Statement warning at mult242.vhd(29): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult242.vhd(29) " "Warning: VHDL Process Statement warning at mult242.vhd(29): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult242.vhd(29) " "Warning: VHDL Process Statement warning at mult242.vhd(29): signal s3 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult242.vhd(29) " "Warning: VHDL Process Statement warning at mult242.vhd(29): signal s4 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult242.vhd(32) " "Warning: VHDL Process Statement warning at mult242.vhd(32): signal s1 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult242.vhd(32) " "Warning: VHDL Process Statement warning at mult242.vhd(32): signal s2 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult242.vhd(32) " "Warning: VHDL Process Statement warning at mult242.vhd(32): signal s3 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult242.vhd(32) " "Warning: VHDL Process Statement warning at mult242.vhd(32): signal s4 is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 32 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult162:inst33\|Dout\[0\]~reg0 data_in GND " "Warning: Reduced register mult162:inst33\|Dout\[0\]~reg0 with stuck data_in port to stuck value GND" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult162.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult52:inst31\|Dout\[0\]~reg0 data_in GND " "Warning: Reduced register mult52:inst31\|Dout\[0\]~reg0 with stuck data_in port to stuck value GND" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult52.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult52.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult12:inst26\|Dout\[0\]~reg0 data_in GND " "Warning: Reduced register mult12:inst26\|Dout\[0\]~reg0 with stuck data_in port to stuck value GND" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/mult12.vhd" 8 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "dff89:inst34\|Dout\[7\]~reg0 dff89:inst34\|Dout\[8\]~reg0 " "Info: Duplicate register dff89:inst34\|Dout\[7\]~reg0 merged to single register dff89:inst34\|Dout\[8\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[7\]~reg0 dff89:inst34\|Dout\[8\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[7\]~reg0 merged to single register dff89:inst34\|Dout\[8\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[6\]~reg0 dff89:inst34\|Dout\[6\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[6\]~reg0 merged to single register dff89:inst34\|Dout\[6\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[5\]~reg0 dff89:inst34\|Dout\[5\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[5\]~reg0 merged to single register dff89:inst34\|Dout\[5\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[4\]~reg0 dff89:inst34\|Dout\[4\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[4\]~reg0 merged to single register dff89:inst34\|Dout\[4\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[3\]~reg0 dff89:inst34\|Dout\[3\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[3\]~reg0 merged to single register dff89:inst34\|Dout\[3\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[2\]~reg0 dff89:inst34\|Dout\[2\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[2\]~reg0 merged to single register dff89:inst34\|Dout\[2\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[1\]~reg0 dff89:inst34\|Dout\[1\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[1\]~reg0 merged to single register dff89:inst34\|Dout\[1\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[0\]~reg0 dff89:inst34\|Dout\[0\]~reg0 " "Info: Duplicate register dff8:inst10\|Dout\[0\]~reg0 merged to single register dff89:inst34\|Dout\[0\]~reg0" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "775 " "Info: Implemented 775 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "757 " "Info: Implemented 757 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 47 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 18 15:22:33 2007 " "Info: Processing ended: Fri May 18 15:22:33 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}