📄 fir.tan.qmsg
字号:
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Dout\[6\] add888:inst44\|Dout\[6\]~reg0 5.403 ns register " "Info: tco from clock clk to destination pin Dout\[6\] through register add888:inst44\|Dout\[6\]~reg0 is 5.403 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.121 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK Pin_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 435; CLK Node = 'clk'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.547 ns) 2.121 ns add888:inst44\|Dout\[6\]~reg0 2 REG LC_X15_Y13_N6 1 " "Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X15_Y13_N6; Fanout = 1; REG Node = 'add888:inst44\|Dout\[6\]~reg0'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.991 ns" { clk add888:inst44|Dout[6]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.07 % " "Info: Total cell delay = 1.677 ns ( 79.07 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns 20.93 % " "Info: Total interconnect delay = 0.444 ns ( 20.93 % )" { } { } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.121 ns" { clk add888:inst44|Dout[6]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.109 ns + Longest register pin " "Info: + Longest register to pin delay is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add888:inst44\|Dout\[6\]~reg0 1 REG LC_X15_Y13_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y13_N6; Fanout = 1; REG Node = 'add888:inst44\|Dout\[6\]~reg0'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { add888:inst44|Dout[6]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.487 ns) + CELL(1.622 ns) 3.109 ns Dout\[6\] 2 PIN Pin_78 0 " "Info: 2: + IC(1.487 ns) + CELL(1.622 ns) = 3.109 ns; Loc. = Pin_78; Fanout = 0; PIN Node = 'Dout\[6\]'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "3.109 ns" { add888:inst44|Dout[6]~reg0 Dout[6] } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 1024 1512 1688 1040 "Dout\[7..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 52.17 % " "Info: Total cell delay = 1.622 ns ( 52.17 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.487 ns 47.83 % " "Info: Total interconnect delay = 1.487 ns ( 47.83 % )" { } { } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "3.109 ns" { add888:inst44|Dout[6]~reg0 Dout[6] } "NODE_NAME" } } } } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.121 ns" { clk add888:inst44|Dout[6]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "3.109 ns" { add888:inst44|Dout[6]~reg0 Dout[6] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "dff8:inst2\|Dout\[7\]~reg0 Din\[7\] clk -3.044 ns register " "Info: th for register dff8:inst2\|Dout\[7\]~reg0 (data pin = Din\[7\], clock pin = clk) is -3.044 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.082 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK Pin_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 435; CLK Node = 'clk'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.547 ns) 2.082 ns dff8:inst2\|Dout\[7\]~reg0 2 REG LC_X11_Y2_N2 5 " "Info: 2: + IC(0.405 ns) + CELL(0.547 ns) = 2.082 ns; Loc. = LC_X11_Y2_N2; Fanout = 5; REG Node = 'dff8:inst2\|Dout\[7\]~reg0'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.952 ns" { clk dff8:inst2|Dout[7]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 80.55 % " "Info: Total cell delay = 1.677 ns ( 80.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.405 ns 19.45 % " "Info: Total interconnect delay = 0.405 ns ( 19.45 % )" { } { } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.082 ns" { clk dff8:inst2|Dout[7]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" { } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.138 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Din\[7\] 1 PIN Pin_37 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = Pin_37; Fanout = 5; PIN Node = 'Din\[7\]'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { Din[7] } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 120 -64 104 136 "Din\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.914 ns) + CELL(0.089 ns) 5.138 ns dff8:inst2\|Dout\[7\]~reg0 2 REG LC_X11_Y2_N2 5 " "Info: 2: + IC(3.914 ns) + CELL(0.089 ns) = 5.138 ns; Loc. = LC_X11_Y2_N2; Fanout = 5; REG Node = 'dff8:inst2\|Dout\[7\]~reg0'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "4.003 ns" { Din[7] dff8:inst2|Dout[7]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/dff8.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns 23.82 % " "Info: Total cell delay = 1.224 ns ( 23.82 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.914 ns 76.18 % " "Info: Total interconnect delay = 3.914 ns ( 76.18 % )" { } { } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "5.138 ns" { Din[7] dff8:inst2|Dout[7]~reg0 } "NODE_NAME" } } } } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.082 ns" { clk dff8:inst2|Dout[7]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "5.138 ns" { Din[7] dff8:inst2|Dout[7]~reg0 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk Dout\[1\] add888:inst44\|Dout\[1\]~reg0 4.908 ns register " "Info: Minimum tco from clock clk to destination pin Dout\[1\] through register add888:inst44\|Dout\[1\]~reg0 is 4.908 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.121 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK Pin_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 435; CLK Node = 'clk'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.547 ns) 2.121 ns add888:inst44\|Dout\[1\]~reg0 2 REG LC_X15_Y13_N1 1 " "Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X15_Y13_N1; Fanout = 1; REG Node = 'add888:inst44\|Dout\[1\]~reg0'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.991 ns" { clk add888:inst44|Dout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.07 % " "Info: Total cell delay = 1.677 ns ( 79.07 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns 20.93 % " "Info: Total interconnect delay = 0.444 ns ( 20.93 % )" { } { } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.121 ns" { clk add888:inst44|Dout[1]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.614 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add888:inst44\|Dout\[1\]~reg0 1 REG LC_X15_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y13_N1; Fanout = 1; REG Node = 'add888:inst44\|Dout\[1\]~reg0'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { add888:inst44|Dout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/add888.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(1.622 ns) 2.614 ns Dout\[1\] 2 PIN Pin_87 0 " "Info: 2: + IC(0.992 ns) + CELL(1.622 ns) = 2.614 ns; Loc. = Pin_87; Fanout = 0; PIN Node = 'Dout\[1\]'" { } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.614 ns" { add888:inst44|Dout[1]~reg0 Dout[1] } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 1024 1512 1688 1040 "Dout\[7..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 62.05 % " "Info: Total cell delay = 1.622 ns ( 62.05 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.992 ns 37.95 % " "Info: Total interconnect delay = 0.992 ns ( 37.95 % )" { } { } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.614 ns" { add888:inst44|Dout[1]~reg0 Dout[1] } "NODE_NAME" } } } } 0} } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.121 ns" { clk add888:inst44|Dout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.614 ns" { add888:inst44|Dout[1]~reg0 Dout[1] } "NODE_NAME" } } } } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -