fir.tan.qmsg

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } { "d:/quartus/quartus4/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/quartus4/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dff89:inst34\|Dout\[3\]~reg0 register mult242:inst40\|Dout\[15\]~reg0 121.51 MHz 8.23 ns Internal " "Info: Clock clk has Internal fmax of 121.51 MHz between source register dff89:inst34\|Dout\[3\]~reg0 and destination register mult242:inst40\|Dout\[15\]~reg0 (period= 8.23 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.028 ns + Longest register register " "Info: + Longest register to register delay is 8.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff89:inst34\|Dout\[3\]~reg0 1 REG LC_X9_Y11_N7 30 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y11_N7; Fanout = 30; REG Node = 'dff89:inst34\|Dout\[3\]~reg0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { dff89:inst34|Dout[3]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.434 ns) 1.353 ns mult242:inst40\|i~71COUT0 2 COMB LC_X10_Y11_N3 2 " "Info: 2: + IC(0.919 ns) + CELL(0.434 ns) = 1.353 ns; Loc. = LC_X10_Y11_N3; Fanout = 2; COMB Node = 'mult242:inst40\|i~71COUT0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "1.353 ns" { dff89:inst34|Dout[3]~reg0 mult242:inst40|i~71COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 1.490 ns mult242:inst40\|i~72COUT 3 COMB LC_X10_Y11_N4 5 " "Info: 3: + IC(0.000 ns) + CELL(0.137 ns) = 1.490 ns; Loc. = LC_X10_Y11_N4; Fanout = 5; COMB Node = 'mult242:inst40\|i~72COUT'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.137 ns" { mult242:inst40|i~71COUT0 mult242:inst40|i~72COUT } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 1.968 ns mult242:inst40\|i~73 4 COMB LC_X10_Y11_N5 3 " "Info: 4: + IC(0.000 ns) + CELL(0.478 ns) = 1.968 ns; Loc. = LC_X10_Y11_N5; Fanout = 3; COMB Node = 'mult242:inst40\|i~73'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.478 ns" { mult242:inst40|i~72COUT mult242:inst40|i~73 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.333 ns) 3.228 ns mult242:inst40\|i~85COUT1 5 COMB LC_X11_Y10_N1 2 " "Info: 5: + IC(0.927 ns) + CELL(0.333 ns) = 3.228 ns; Loc. = LC_X11_Y10_N1; Fanout = 2; COMB Node = 'mult242:inst40\|i~85COUT1'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "1.260 ns" { mult242:inst40|i~73 mult242:inst40|i~85COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 3.290 ns mult242:inst40\|i~86COUT1 6 COMB LC_X11_Y10_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 3.290 ns; Loc. = LC_X11_Y10_N2; Fanout = 2; COMB Node = 'mult242:inst40\|i~86COUT1'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.062 ns" { mult242:inst40|i~85COUT1 mult242:inst40|i~86COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 3.758 ns mult242:inst40\|i~87 7 COMB LC_X11_Y10_N3 3 " "Info: 7: + IC(0.000 ns) + CELL(0.468 ns) = 3.758 ns; Loc. = LC_X11_Y10_N3; Fanout = 3; COMB Node = 'mult242:inst40\|i~87'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.468 ns" { mult242:inst40|i~86COUT1 mult242:inst40|i~87 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.443 ns) 4.729 ns mult242:inst40\|i~100COUT1 8 COMB LC_X12_Y10_N3 2 " "Info: 8: + IC(0.528 ns) + CELL(0.443 ns) = 4.729 ns; Loc. = LC_X12_Y10_N3; Fanout = 2; COMB Node = 'mult242:inst40\|i~100COUT1'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.971 ns" { mult242:inst40|i~87 mult242:inst40|i~100COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 5.197 ns mult242:inst40\|i~101 9 COMB LC_X12_Y10_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(0.468 ns) = 5.197 ns; Loc. = LC_X12_Y10_N4; Fanout = 3; COMB Node = 'mult242:inst40\|i~101'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.468 ns" { mult242:inst40|i~100COUT1 mult242:inst40|i~101 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.968 ns) + CELL(0.443 ns) 6.608 ns mult242:inst40\|i~29COUT1 10 COMB LC_X11_Y12_N5 1 " "Info: 10: + IC(0.968 ns) + CELL(0.443 ns) = 6.608 ns; Loc. = LC_X11_Y12_N5; Fanout = 1; COMB Node = 'mult242:inst40\|i~29COUT1'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "1.411 ns" { mult242:inst40|i~101 mult242:inst40|i~29COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 7.076 ns mult242:inst40\|i~30 11 COMB LC_X11_Y12_N6 1 " "Info: 11: + IC(0.000 ns) + CELL(0.468 ns) = 7.076 ns; Loc. = LC_X11_Y12_N6; Fanout = 1; COMB Node = 'mult242:inst40\|i~30'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.468 ns" { mult242:inst40|i~29COUT1 mult242:inst40|i~30 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.863 ns) + CELL(0.089 ns) 8.028 ns mult242:inst40\|Dout\[15\]~reg0 12 REG LC_X10_Y12_N6 1 " "Info: 12: + IC(0.863 ns) + CELL(0.089 ns) = 8.028 ns; Loc. = LC_X10_Y12_N6; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[15\]~reg0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.952 ns" { mult242:inst40|i~30 mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.823 ns 47.62 % " "Info: Total cell delay = 3.823 ns ( 47.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.205 ns 52.38 % " "Info: Total interconnect delay = 4.205 ns ( 52.38 % )" {  } {  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "8.028 ns" { dff89:inst34|Dout[3]~reg0 mult242:inst40|i~71COUT0 mult242:inst40|i~72COUT mult242:inst40|i~73 mult242:inst40|i~85COUT1 mult242:inst40|i~86COUT1 mult242:inst40|i~87 mult242:inst40|i~100COUT1 mult242:inst40|i~101 mult242:inst40|i~29COUT1 mult242:inst40|i~30 mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.111 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK Pin_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.547 ns) 2.111 ns mult242:inst40\|Dout\[15\]~reg0 2 REG LC_X10_Y12_N6 1 " "Info: 2: + IC(0.434 ns) + CELL(0.547 ns) = 2.111 ns; Loc. = LC_X10_Y12_N6; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[15\]~reg0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.981 ns" { clk mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.44 % " "Info: Total cell delay = 1.677 ns ( 79.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.434 ns 20.56 % " "Info: Total interconnect delay = 0.434 ns ( 20.56 % )" {  } {  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.111 ns" { clk mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.111 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK Pin_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.547 ns) 2.111 ns dff89:inst34\|Dout\[3\]~reg0 2 REG LC_X9_Y11_N7 30 " "Info: 2: + IC(0.434 ns) + CELL(0.547 ns) = 2.111 ns; Loc. = LC_X9_Y11_N7; Fanout = 30; REG Node = 'dff89:inst34\|Dout\[3\]~reg0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.981 ns" { clk dff89:inst34|Dout[3]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.44 % " "Info: Total cell delay = 1.677 ns ( 79.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.434 ns 20.56 % " "Info: Total interconnect delay = 0.434 ns ( 20.56 % )" {  } {  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.111 ns" { clk dff89:inst34|Dout[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.111 ns" { clk mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.111 ns" { clk dff89:inst34|Dout[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/dff89.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/mult242.vhd" 38 -1 0 } }  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "8.028 ns" { dff89:inst34|Dout[3]~reg0 mult242:inst40|i~71COUT0 mult242:inst40|i~72COUT mult242:inst40|i~73 mult242:inst40|i~85COUT1 mult242:inst40|i~86COUT1 mult242:inst40|i~87 mult242:inst40|i~100COUT1 mult242:inst40|i~101 mult242:inst40|i~29COUT1 mult242:inst40|i~30 mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.111 ns" { clk mult242:inst40|Dout[15]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.111 ns" { clk dff89:inst34|Dout[3]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "add889:inst18\|Dout\[8\]~reg0 Din\[4\] clk 5.025 ns register " "Info: tsu for register add889:inst18\|Dout\[8\]~reg0 (data pin = Din\[4\], clock pin = clk) is 5.025 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.078 ns + Longest pin register " "Info: + Longest pin to register delay is 7.078 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Din\[4\] 1 PIN Pin_38 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = Pin_38; Fanout = 3; PIN Node = 'Din\[4\]'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { Din[4] } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 120 -64 104 136 "Din\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.848 ns) + CELL(0.449 ns) 6.432 ns add889:inst18\|Dout\[4\]~reg0COUT 2 COMB LC_X10_Y4_N4 4 " "Info: 2: + IC(4.848 ns) + CELL(0.449 ns) = 6.432 ns; Loc. = LC_X10_Y4_N4; Fanout = 4; COMB Node = 'add889:inst18\|Dout\[4\]~reg0COUT'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "5.297 ns" { Din[4] add889:inst18|Dout[4]~reg0COUT } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 7.078 ns add889:inst18\|Dout\[8\]~reg0 3 REG LC_X10_Y4_N8 22 " "Info: 3: + IC(0.000 ns) + CELL(0.646 ns) = 7.078 ns; Loc. = LC_X10_Y4_N8; Fanout = 22; REG Node = 'add889:inst18\|Dout\[8\]~reg0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.646 ns" { add889:inst18|Dout[4]~reg0COUT add889:inst18|Dout[8]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.230 ns 31.51 % " "Info: Total cell delay = 2.230 ns ( 31.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.848 ns 68.49 % " "Info: Total interconnect delay = 4.848 ns ( 68.49 % )" {  } {  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "7.078 ns" { Din[4] add889:inst18|Dout[4]~reg0COUT add889:inst18|Dout[8]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.082 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK Pin_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" "" "" { Schematic "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.547 ns) 2.082 ns add889:inst18\|Dout\[8\]~reg0 2 REG LC_X10_Y4_N8 22 " "Info: 2: + IC(0.405 ns) + CELL(0.547 ns) = 2.082 ns; Loc. = LC_X10_Y4_N8; Fanout = 22; REG Node = 'add889:inst18\|Dout\[8\]~reg0'" {  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "0.952 ns" { clk add889:inst18|Dout[8]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" "" "" { Text "C:/Documents and Settings/sui/My Documents/eda/隋远106040514/fir/add889.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 80.55 % " "Info: Total cell delay = 1.677 ns ( 80.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.405 ns 19.45 % " "Info: Total interconnect delay = 0.405 ns ( 19.45 % )" {  } {  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.082 ns" { clk add889:inst18|Dout[8]~reg0 } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "7.078 ns" { Din[4] add889:inst18|Dout[4]~reg0COUT add889:inst18|Dout[8]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" "" "" { Report "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/sui/My Documents/eda/shiyan/fir/db/fir.quartus_db" { Floorplan "" "" "2.082 ns" { clk add889:inst18|Dout[8]~reg0 } "NODE_NAME" } } }  } 0}