pro3.tan.rpt

VHDL spi源代码内核介绍

+--------------------------------------------------------------------------------+
; tco                                                                            ;
+-------+--------------+------------+--------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To       ; From Clock ;
+-------+--------------+------------+--------------------+----------+------------+
; N/A   ; None         ; 11.750 ns  ; sipo:inst1|q[6]    ; d_out[6] ; clk        ;
; N/A   ; None         ; 11.746 ns  ; sipo:inst1|q[0]    ; d_out[0] ; clk        ;
; N/A   ; None         ; 11.741 ns  ; sipo:inst1|q[7]    ; d_out[7] ; clk        ;
; N/A   ; None         ; 11.452 ns  ; sipo:inst1|q[1]    ; d_out[1] ; clk        ;
; N/A   ; None         ; 11.450 ns  ; sipo:inst1|q[3]    ; d_out[3] ; clk        ;
; N/A   ; None         ; 11.440 ns  ; sipo:inst1|q[5]    ; d_out[5] ; clk        ;
; N/A   ; None         ; 11.306 ns  ; sipo:inst1|q[2]    ; d_out[2] ; clk        ;
; N/A   ; None         ; 11.303 ns  ; sipo:inst1|q[4]    ; d_out[4] ; clk        ;
; N/A   ; None         ; 11.258 ns  ; sopi:inst|data_out ; mosi     ; clk        ;
+-------+--------------+------------+--------------------+----------+------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 9.061 ns        ; ssl  ; mosi ;
+-------+-------------------+-----------------+------+------+


+-----------------------------------------------------------------------------------+
; th                                                                                ;
+---------------+-------------+-----------+------------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To              ; To Clock ;
+---------------+-------------+-----------+------------+-----------------+----------+
; N/A           ; None        ; -0.678 ns ; miso       ; sipo:inst1|q[0] ; clk      ;
; N/A           ; None        ; -4.267 ns ; data_in[0] ; sopi:inst|q[0]  ; load     ;
+---------------+-------------+-----------+------------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jul 31 23:24:56 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pro3 -c pro3 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "sopi:inst|q[0]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "load" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "sopi:inst|q[1]" and destination register "sopi:inst|q[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.495 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst|q[1]'
            Info: 2: + IC(0.757 ns) + CELL(0.738 ns) = 1.495 ns; Loc. = LC_X34_Y2_N8; Fanout = 1; REG Node = 'sopi:inst|q[2]'
            Info: Total cell delay = 0.738 ns ( 49.36 % )
            Info: Total interconnect delay = 0.757 ns ( 50.64 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 7.766 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'
                Info: 2: + IC(5.586 ns) + CELL(0.711 ns) = 7.766 ns; Loc. = LC_X34_Y2_N8; Fanout = 1; REG Node = 'sopi:inst|q[2]'
                Info: Total cell delay = 2.180 ns ( 28.07 % )
                Info: Total interconnect delay = 5.586 ns ( 71.93 % )
            Info: - Longest clock path from clock "clk" to source register is 7.766 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'
                Info: 2: + IC(5.586 ns) + CELL(0.711 ns) = 7.766 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst|q[1]'
                Info: Total cell delay = 2.180 ns ( 28.07 % )
                Info: Total interconnect delay = 5.586 ns ( 71.93 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "sopi:inst|q[0]" (data pin = "data_in[0]", clock pin = "load") is 5.226 ns
    Info: + Longest pin to register delay is 7.149 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_119; Fanout = 1; PIN Node = 'data_in[0]'
        Info: 2: + IC(5.084 ns) + CELL(0.590 ns) = 7.149 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst|q[0]'
        Info: Total cell delay = 2.065 ns ( 28.89 % )
        Info: Total interconnect delay = 5.084 ns ( 71.11 % )
    Info: + Micro setup delay of destination is 0.959 ns
    Info: - Shortest clock path from clock "load" to destination register is 2.882 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'load'
        Info: 2: + IC(1.299 ns) + CELL(0.114 ns) = 2.882 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst|q[0]'
        Info: Total cell delay = 1.583 ns ( 54.93 % )
        Info: Total interconnect delay = 1.299 ns ( 45.07 % )
Info: tco from clock "clk" to destination pin "d_out[6]" through register "sipo:inst1|q[6]" is 11.750 ns
    Info: + Longest clock path from clock "clk" to source register is 7.814 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(5.634 ns) + CELL(0.711 ns) = 7.814 ns; Loc. = LC_X34_Y20_N7; Fanout = 2; REG Node = 'sipo:inst1|q[6]'
        Info: Total cell delay = 2.180 ns ( 27.90 % )
        Info: Total interconnect delay = 5.634 ns ( 72.10 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.712 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y20_N7; Fanout = 2; REG Node = 'sipo:inst1|q[6]'
        Info: 2: + IC(1.588 ns) + CELL(2.124 ns) = 3.712 ns; Loc. = PIN_176; Fanout = 0; PIN Node = 'd_out[6]'
        Info: Total cell delay = 2.124 ns ( 57.22 % )
        Info: Total interconnect delay = 1.588 ns ( 42.78 % )
Info: Longest tpd from source pin "ssl" to destination pin "mosi" is 9.061 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'ssl'
    Info: 2: + IC(5.518 ns) + CELL(2.074 ns) = 9.061 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'mosi'
    Info: Total cell delay = 3.543 ns ( 39.10 % )
    Info: Total interconnect delay = 5.518 ns ( 60.90 % )
Info: th for register "sipo:inst1|q[0]" (data pin = "miso", clock pin = "clk") is -0.678 ns
    Info: + Longest clock path from clock "clk" to destination register is 7.814 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(5.634 ns) + CELL(0.711 ns) = 7.814 ns; Loc. = LC_X34_Y20_N8; Fanout = 2; REG Node = 'sipo:inst1|q[0]'
        Info: Total cell delay = 2.180 ns ( 27.90 % )
        Info: Total interconnect delay = 5.634 ns ( 72.10 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.507 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; PIN Node = 'miso'
        Info: 2: + IC(6.729 ns) + CELL(0.309 ns) = 8.507 ns; Loc. = LC_X34_Y20_N8; Fanout = 2; REG Node = 'sipo:inst1|q[0]'
        Info: Total cell delay = 1.778 ns ( 20.90 % )
        Info: Total interconnect delay = 6.729 ns ( 79.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Mon Jul 31 23:24:56 2006
    Info: Elapsed time: 00:00:01