count10.tan.qmsg

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "pin_name register register inst3 inst3 320.1 MHz Internal " "Info: Clock \"pin_name\" Internal fmax is restricted to 320.1 MHz between source register \"inst3\" and destination register \"inst3\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.562 ns 1.562 ns 3.124 ns " "Info: fmax restricted to Clock High delay (1.562 ns) plus Clock Low delay (1.562 ns) : restricted to 3.124 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.134 ns + Longest register register " "Info: + Longest register to register delay is 1.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LC_X1_Y8_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.653 ns) 1.134 ns inst3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(0.481 ns) + CELL(0.653 ns) = 1.134 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.134 ns" { inst3 inst3 } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.653 ns ( 57.58 % ) " "Info: Total cell delay = 0.653 ns ( 57.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.481 ns ( 42.42 % ) " "Info: Total interconnect delay = 0.481 ns ( 42.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.134 ns" { inst3 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "1.134 ns" { inst3 inst3 } { 0.000ns 0.481ns } { 0.000ns 0.653ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_name destination 2.566 ns + Shortest register " "Info: + Shortest clock path from clock \"pin_name\" to destination register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns pin_name 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'pin_name'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { pin_name } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 104 -128 40 120 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns inst3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { pin_name inst3 } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst3 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_name source 2.566 ns - Longest register " "Info: - Longest clock path from clock \"pin_name\" to source register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns pin_name 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'pin_name'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { pin_name } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 104 -128 40 120 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns inst3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { pin_name inst3 } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst3 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst3 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst3 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.134 ns" { inst3 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "1.134 ns" { inst3 inst3 } { 0.000ns 0.481ns } { 0.000ns 0.653ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst3 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst3 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "" { inst3 } {  } {  } } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 864 928 88 "inst3" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pin_name qb inst2 6.180 ns register " "Info: tco from clock \"pin_name\" to destination pin \"qb\" through register \"inst2\" is 6.180 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_name source 2.566 ns + Longest register " "Info: + Longest clock path from clock \"pin_name\" to source register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns pin_name 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'pin_name'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { pin_name } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 104 -128 40 120 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns inst2 2 REG LC_X1_Y8_N9 3 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y8_N9; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { pin_name inst2 } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 648 712 88 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst2 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst2 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 648 712 88 "inst2" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.416 ns + Longest register pin " "Info: + Longest register to pin delay is 3.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst2 1 REG LC_X1_Y8_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N9; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst2 } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 8 648 712 88 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(1.879 ns) 3.416 ns qb 2 PIN PIN_23 0 " "Info: 2: + IC(1.537 ns) + CELL(1.879 ns) = 3.416 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'qb'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.416 ns" { inst2 qb } "NODE_NAME" } } { "count10.bdf" "" { Schematic "D:/Quartus II/count10/count10.bdf" { { 152 744 920 168 "qb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.879 ns ( 55.01 % ) " "Info: Total cell delay = 1.879 ns ( 55.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 44.99 % ) " "Info: Total interconnect delay = 1.537 ns ( 44.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.416 ns" { inst2 qb } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "3.416 ns" { inst2 qb } { 0.000ns 1.537ns } { 0.000ns 1.879ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { pin_name inst2 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { pin_name pin_name~out0 inst2 } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.416 ns" { inst2 qb } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "3.416 ns" { inst2 qb } { 0.000ns 1.537ns } { 0.000ns 1.879ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 01 23:06:58 2008 " "Info: Processing ended: Tue Apr 01 23:06:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}