📄 count10.tan.rpt
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Timing Analyzer report for count10
Tue Apr 01 23:06:58 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'pin_name'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------+-------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.180 ns ; inst2 ; qb ; pin_name ; -- ; 0 ;
; Clock Setup: 'pin_name' ; N/A ; None ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst3 ; inst3 ; pin_name ; pin_name ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C7 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; pin_name ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pin_name' ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst3 ; inst3 ; pin_name ; pin_name ; None ; None ; 1.134 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst1 ; inst2 ; pin_name ; pin_name ; None ; None ; 1.042 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst ; inst3 ; pin_name ; pin_name ; None ; None ; 1.041 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst1 ; inst1 ; pin_name ; pin_name ; None ; None ; 1.034 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst2 ; inst3 ; pin_name ; pin_name ; None ; None ; 0.919 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst2 ; inst2 ; pin_name ; pin_name ; None ; None ; 0.918 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst ; inst1 ; pin_name ; pin_name ; None ; None ; 0.797 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst1 ; inst3 ; pin_name ; pin_name ; None ; None ; 0.797 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst ; inst2 ; pin_name ; pin_name ; None ; None ; 0.794 ns ;
; N/A ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; inst ; inst ; pin_name ; pin_name ; None ; None ; 0.793 ns ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+----+------------+
; N/A ; None ; 6.180 ns ; inst2 ; qb ; pin_name ;
; N/A ; None ; 6.042 ns ; inst3 ; qa ; pin_name ;
; N/A ; None ; 5.655 ns ; inst1 ; qc ; pin_name ;
; N/A ; None ; 5.652 ns ; inst ; qd ; pin_name ;
+-------+--------------+------------+-------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Apr 01 23:06:57 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count10 -c count10 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "pin_name" is an undefined clock
Info: Clock "pin_name" Internal fmax is restricted to 320.1 MHz between source register "inst3" and destination register "inst3"
Info: fmax restricted to Clock High delay (1.562 ns) plus Clock Low delay (1.562 ns) : restricted to 3.124 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.134 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'
Info: 2: + IC(0.481 ns) + CELL(0.653 ns) = 1.134 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'
Info: Total cell delay = 0.653 ns ( 57.58 % )
Info: Total interconnect delay = 0.481 ns ( 42.42 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "pin_name" to destination register is 2.566 ns
Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'pin_name'
Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'
Info: Total cell delay = 1.928 ns ( 75.14 % )
Info: Total interconnect delay = 0.638 ns ( 24.86 % )
Info: - Longest clock path from clock "pin_name" to source register is 2.566 ns
Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'pin_name'
Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'inst3'
Info: Total cell delay = 1.928 ns ( 75.14 % )
Info: Total interconnect delay = 0.638 ns ( 24.86 % )
Info: + Micro clock to output delay of source is 0.198 ns
Info: + Micro setup delay of destination is 0.033 ns
Info: tco from clock "pin_name" to destination pin "qb" through register "inst2" is 6.180 ns
Info: + Longest clock path from clock "pin_name" to source register is 2.566 ns
Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'pin_name'
Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y8_N9; Fanout = 3; REG Node = 'inst2'
Info: Total cell delay = 1.928 ns ( 75.14 % )
Info: Total interconnect delay = 0.638 ns ( 24.86 % )
Info: + Micro clock to output delay of source is 0.198 ns
Info: + Longest register to pin delay is 3.416 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N9; Fanout = 3; REG Node = 'inst2'
Info: 2: + IC(1.537 ns) + CELL(1.879 ns) = 3.416 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'qb'
Info: Total cell delay = 1.879 ns ( 55.01 % )
Info: Total interconnect delay = 1.537 ns ( 44.99 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Apr 01 23:06:58 2008
Info: Elapsed time: 00:00:01
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