moore.tan.qmsg

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

{ "Info" "ITDB_TSU_RESULT" "PresentState\[1\] con cp 3.330 ns register " "Info: tsu for register \"PresentState\[1\]\" (data pin = \"con\", clock pin = \"cp\") is 3.330 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.863 ns + Longest pin register " "Info: + Longest pin to register delay is 5.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns con 1 PIN PIN_50 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_50; Fanout = 2; PIN Node = 'con'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { con } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.027 ns) + CELL(0.537 ns) 5.863 ns PresentState\[1\] 2 REG LC_X1_Y4_N9 3 " "Info: 2: + IC(4.027 ns) + CELL(0.537 ns) = 5.863 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.564 ns" { con PresentState[1] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 31.32 % ) " "Info: Total cell delay = 1.836 ns ( 31.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.027 ns ( 68.68 % ) " "Info: Total interconnect delay = 4.027 ns ( 68.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.863 ns" { con PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.863 ns" { con con~out0 PresentState[1] } { 0.000ns 0.000ns 4.027ns } { 0.000ns 1.299ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.566 ns - Shortest register " "Info: - Shortest clock path from clock \"cp\" to destination register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns cp 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns PresentState\[1\] 2 REG LC_X1_Y4_N9 3 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { cp PresentState[1] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.863 ns" { con PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.863 ns" { con con~out0 PresentState[1] } { 0.000ns 0.000ns 4.027ns } { 0.000ns 1.299ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp flag PresentState\[0\] 6.852 ns register " "Info: tco from clock \"cp\" to destination pin \"flag\" through register \"PresentState\[0\]\" is 6.852 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.566 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to source register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns cp 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns PresentState\[0\] 2 REG LC_X1_Y4_N5 4 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState\[0\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { cp PresentState[0] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[0] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.088 ns + Longest register pin " "Info: + Longest register to pin delay is 4.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PresentState\[0\] 1 REG LC_X1_Y4_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState\[0\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { PresentState[0] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.390 ns) 0.857 ns Mux2~11 2 COMB LC_X1_Y4_N4 1 " "Info: 2: + IC(0.467 ns) + CELL(0.390 ns) = 0.857 ns; Loc. = LC_X1_Y4_N4; Fanout = 1; COMB Node = 'Mux2~11'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.857 ns" { PresentState[0] Mux2~11 } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.352 ns) + CELL(1.879 ns) 4.088 ns flag 3 PIN PIN_46 0 " "Info: 3: + IC(1.352 ns) + CELL(1.879 ns) = 4.088 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'flag'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.231 ns" { Mux2~11 flag } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.269 ns ( 55.50 % ) " "Info: Total cell delay = 2.269 ns ( 55.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.819 ns ( 44.50 % ) " "Info: Total interconnect delay = 1.819 ns ( 44.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.088 ns" { PresentState[0] Mux2~11 flag } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.088 ns" { PresentState[0] Mux2~11 flag } { 0.000ns 0.467ns 1.352ns } { 0.000ns 0.390ns 1.879ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[0] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.088 ns" { PresentState[0] Mux2~11 flag } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.088 ns" { PresentState[0] Mux2~11 flag } { 0.000ns 0.467ns 1.352ns } { 0.000ns 0.390ns 1.879ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "PresentState\[0\] con cp -3.282 ns register " "Info: th for register \"PresentState\[0\]\" (data pin = \"con\", clock pin = \"cp\") is -3.282 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.566 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns cp 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns PresentState\[0\] 2 REG LC_X1_Y4_N5 4 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState\[0\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { cp PresentState[0] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[0] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.861 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns con 1 PIN PIN_50 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_50; Fanout = 2; PIN Node = 'con'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { con } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.025 ns) + CELL(0.537 ns) 5.861 ns PresentState\[0\] 2 REG LC_X1_Y4_N5 4 " "Info: 2: + IC(4.025 ns) + CELL(0.537 ns) = 5.861 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState\[0\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.562 ns" { con PresentState[0] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 31.33 % ) " "Info: Total cell delay = 1.836 ns ( 31.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.025 ns ( 68.67 % ) " "Info: Total interconnect delay = 4.025 ns ( 68.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.861 ns" { con PresentState[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.861 ns" { con con~out0 PresentState[0] } { 0.000ns 0.000ns 4.025ns } { 0.000ns 1.299ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[0] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.861 ns" { con PresentState[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.861 ns" { con con~out0 PresentState[0] } { 0.000ns 0.000ns 4.025ns } { 0.000ns 1.299ns 0.537ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 01 22:02:11 2008 " "Info: Processing ended: Tue Apr 01 22:02:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}