moore.tan.qmsg

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 01 22:02:11 2008 " "Info: Processing started: Tue Apr 01 22:02:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Moore -c Moore --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Moore -c Moore --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cp " "Info: Assuming node \"cp\" is an undefined clock" {  } { { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 7 -1 0 } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "cp" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cp register register PresentState\[1\] PresentState\[1\] 320.1 MHz Internal " "Info: Clock \"cp\" Internal fmax is restricted to 320.1 MHz between source register \"PresentState\[1\]\" and destination register \"PresentState\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.562 ns 1.562 ns 3.124 ns " "Info: fmax restricted to Clock High delay (1.562 ns) plus Clock Low delay (1.562 ns) : restricted to 3.124 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.909 ns + Longest register register " "Info: + Longest register to register delay is 0.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PresentState\[1\] 1 REG LC_X1_Y4_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { PresentState[1] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.423 ns) 0.909 ns PresentState\[1\] 2 REG LC_X1_Y4_N9 3 " "Info: 2: + IC(0.486 ns) + CELL(0.423 ns) = 0.909 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.909 ns" { PresentState[1] PresentState[1] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.423 ns ( 46.53 % ) " "Info: Total cell delay = 0.423 ns ( 46.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.486 ns ( 53.47 % ) " "Info: Total interconnect delay = 0.486 ns ( 53.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.909 ns" { PresentState[1] PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.909 ns" { PresentState[1] PresentState[1] } { 0.000ns 0.486ns } { 0.000ns 0.423ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.566 ns + Shortest register " "Info: + Shortest clock path from clock \"cp\" to destination register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns cp 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns PresentState\[1\] 2 REG LC_X1_Y4_N9 3 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { cp PresentState[1] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.566 ns - Longest register " "Info: - Longest clock path from clock \"cp\" to source register is 2.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns cp 1 CLK PIN_29 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.629 ns) 2.566 ns PresentState\[1\] 2 REG LC_X1_Y4_N9 3 " "Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.267 ns" { cp PresentState[1] } "NODE_NAME" } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 75.14 % ) " "Info: Total cell delay = 1.928 ns ( 75.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns ( 24.86 % ) " "Info: Total interconnect delay = 0.638 ns ( 24.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.909 ns" { PresentState[1] PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.909 ns" { PresentState[1] PresentState[1] } { 0.000ns 0.486ns } { 0.000ns 0.423ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.566 ns" { cp PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.566 ns" { cp cp~out0 PresentState[1] } { 0.000ns 0.000ns 0.638ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { PresentState[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "" { PresentState[1] } {  } {  } } } { "Moore.vhd" "" { Text "D:/Quartus II/Moore/Moore.vhd" 18 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}