moore.tan.rpt

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

+-------+--------------+------------+------+-----------------+----------+
; N/A   ; None         ; 3.330 ns   ; con  ; PresentState[1] ; cp       ;
; N/A   ; None         ; 3.328 ns   ; con  ; PresentState[0] ; cp       ;
+-------+--------------+------------+------+-----------------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+-----------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To       ; From Clock ;
+-------+--------------+------------+-----------------+----------+------------+
; N/A   ; None         ; 6.852 ns   ; PresentState[0] ; flag     ; cp         ;
; N/A   ; None         ; 6.739 ns   ; PresentState[1] ; flag     ; cp         ;
; N/A   ; None         ; 5.655 ns   ; PresentState[0] ; state[0] ; cp         ;
; N/A   ; None         ; 5.652 ns   ; PresentState[1] ; state[1] ; cp         ;
+-------+--------------+------------+-----------------+----------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; -3.282 ns ; con  ; PresentState[0] ; cp       ;
; N/A           ; None        ; -3.284 ns ; con  ; PresentState[1] ; cp       ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 01 22:02:11 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Moore -c Moore --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" Internal fmax is restricted to 320.1 MHz between source register "PresentState[1]" and destination register "PresentState[1]"
    Info: fmax restricted to Clock High delay (1.562 ns) plus Clock Low delay (1.562 ns) : restricted to 3.124 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.909 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState[1]'
            Info: 2: + IC(0.486 ns) + CELL(0.423 ns) = 0.909 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState[1]'
            Info: Total cell delay = 0.423 ns ( 46.53 % )
            Info: Total interconnect delay = 0.486 ns ( 53.47 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cp" to destination register is 2.566 ns
                Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'
                Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState[1]'
                Info: Total cell delay = 1.928 ns ( 75.14 % )
                Info: Total interconnect delay = 0.638 ns ( 24.86 % )
            Info: - Longest clock path from clock "cp" to source register is 2.566 ns
                Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'
                Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState[1]'
                Info: Total cell delay = 1.928 ns ( 75.14 % )
                Info: Total interconnect delay = 0.638 ns ( 24.86 % )
        Info: + Micro clock to output delay of source is 0.198 ns
        Info: + Micro setup delay of destination is 0.033 ns
Info: tsu for register "PresentState[1]" (data pin = "con", clock pin = "cp") is 3.330 ns
    Info: + Longest pin to register delay is 5.863 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_50; Fanout = 2; PIN Node = 'con'
        Info: 2: + IC(4.027 ns) + CELL(0.537 ns) = 5.863 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState[1]'
        Info: Total cell delay = 1.836 ns ( 31.32 % )
        Info: Total interconnect delay = 4.027 ns ( 68.68 % )
    Info: + Micro setup delay of destination is 0.033 ns
    Info: - Shortest clock path from clock "cp" to destination register is 2.566 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'
        Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N9; Fanout = 3; REG Node = 'PresentState[1]'
        Info: Total cell delay = 1.928 ns ( 75.14 % )
        Info: Total interconnect delay = 0.638 ns ( 24.86 % )
Info: tco from clock "cp" to destination pin "flag" through register "PresentState[0]" is 6.852 ns
    Info: + Longest clock path from clock "cp" to source register is 2.566 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'
        Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState[0]'
        Info: Total cell delay = 1.928 ns ( 75.14 % )
        Info: Total interconnect delay = 0.638 ns ( 24.86 % )
    Info: + Micro clock to output delay of source is 0.198 ns
    Info: + Longest register to pin delay is 4.088 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState[0]'
        Info: 2: + IC(0.467 ns) + CELL(0.390 ns) = 0.857 ns; Loc. = LC_X1_Y4_N4; Fanout = 1; COMB Node = 'Mux2~11'
        Info: 3: + IC(1.352 ns) + CELL(1.879 ns) = 4.088 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'flag'
        Info: Total cell delay = 2.269 ns ( 55.50 % )
        Info: Total interconnect delay = 1.819 ns ( 44.50 % )
Info: th for register "PresentState[0]" (data pin = "con", clock pin = "cp") is -3.282 ns
    Info: + Longest clock path from clock "cp" to destination register is 2.566 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 2; CLK Node = 'cp'
        Info: 2: + IC(0.638 ns) + CELL(0.629 ns) = 2.566 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState[0]'
        Info: Total cell delay = 1.928 ns ( 75.14 % )
        Info: Total interconnect delay = 0.638 ns ( 24.86 % )
    Info: + Micro hold delay of destination is 0.013 ns
    Info: - Shortest pin to register delay is 5.861 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_50; Fanout = 2; PIN Node = 'con'
        Info: 2: + IC(4.025 ns) + CELL(0.537 ns) = 5.861 ns; Loc. = LC_X1_Y4_N5; Fanout = 4; REG Node = 'PresentState[0]'
        Info: Total cell delay = 1.836 ns ( 31.33 % )
        Info: Total interconnect delay = 4.025 ns ( 68.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Apr 01 22:02:11 2008
    Info: Elapsed time: 00:00:01