count_10.tan.rpt

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; 3.231 ns   ; en   ; q[3] ; clk      ;
; N/A   ; None         ; 3.231 ns   ; en   ; q[2] ; clk      ;
; N/A   ; None         ; 3.231 ns   ; en   ; q[0] ; clk      ;
; N/A   ; None         ; 3.231 ns   ; en   ; q[1] ; clk      ;
; N/A   ; None         ; 2.777 ns   ; clr  ; q[3] ; clk      ;
; N/A   ; None         ; 2.777 ns   ; clr  ; q[2] ; clk      ;
; N/A   ; None         ; 2.777 ns   ; clr  ; q[0] ; clk      ;
; N/A   ; None         ; 2.777 ns   ; clr  ; q[1] ; clk      ;
+-------+--------------+------------+------+------+----------+


+------------------------------------------------------------+
; tco                                                        ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A   ; None         ; 6.667 ns   ; q[1] ; qc ; clk        ;
; N/A   ; None         ; 6.436 ns   ; q[3] ; qa ; clk        ;
; N/A   ; None         ; 6.432 ns   ; q[2] ; qb ; clk        ;
; N/A   ; None         ; 6.428 ns   ; q[0] ; qd ; clk        ;
+-------+--------------+------------+------+----+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -1.852 ns ; clr  ; q[0] ; clk      ;
; N/A           ; None        ; -2.392 ns ; clr  ; q[1] ; clk      ;
; N/A           ; None        ; -2.605 ns ; clr  ; q[2] ; clk      ;
; N/A           ; None        ; -2.608 ns ; clr  ; q[3] ; clk      ;
; N/A           ; None        ; -3.121 ns ; en   ; q[3] ; clk      ;
; N/A           ; None        ; -3.121 ns ; en   ; q[2] ; clk      ;
; N/A           ; None        ; -3.121 ns ; en   ; q[0] ; clk      ;
; N/A           ; None        ; -3.121 ns ; en   ; q[1] ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 01 20:19:12 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count_10 -c count_10 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "q[0]" and destination register "q[3]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.377 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N8; Fanout = 6; REG Node = 'q[0]'
            Info: 2: + IC(0.524 ns) + CELL(0.280 ns) = 0.804 ns; Loc. = LC_X1_Y30_N2; Fanout = 3; COMB Node = 'q[3]~306'
            Info: 3: + IC(0.350 ns) + CELL(0.223 ns) = 1.377 ns; Loc. = LC_X1_Y30_N5; Fanout = 4; REG Node = 'q[3]'
            Info: Total cell delay = 0.503 ns ( 36.53 % )
            Info: Total interconnect delay = 0.874 ns ( 63.47 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 4; REG Node = 'q[3]'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 6; REG Node = 'q[0]'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "q[3]" (data pin = "en", clock pin = "clk") is 3.231 ns
    Info: + Longest pin to register delay is 6.155 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C20; Fanout = 1; PIN Node = 'en'
        Info: 2: + IC(3.698 ns) + CELL(0.183 ns) = 4.968 ns; Loc. = LC_X1_Y30_N6; Fanout = 4; COMB Node = 'q[3]~308'
        Info: 3: + IC(0.482 ns) + CELL(0.705 ns) = 6.155 ns; Loc. = LC_X1_Y30_N5; Fanout = 4; REG Node = 'q[3]'
        Info: Total cell delay = 1.975 ns ( 32.09 % )
        Info: Total interconnect delay = 4.180 ns ( 67.91 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 4; REG Node = 'q[3]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
Info: tco from clock "clk" to destination pin "qc" through register "q[1]" is 6.667 ns
    Info: + Longest clock path from clock "clk" to source register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N3; Fanout = 5; REG Node = 'q[1]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.577 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N3; Fanout = 5; REG Node = 'q[1]'
        Info: 2: + IC(1.173 ns) + CELL(2.404 ns) = 3.577 ns; Loc. = PIN_B20; Fanout = 0; PIN Node = 'qc'
        Info: Total cell delay = 2.404 ns ( 67.21 % )
        Info: Total interconnect delay = 1.173 ns ( 32.79 % )
Info: th for register "q[0]" (data pin = "clr", clock pin = "clk") is -1.852 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 6; REG Node = 'q[0]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.886 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_D21; Fanout = 3; PIN Node = 'clr'
        Info: 2: + IC(3.194 ns) + CELL(0.458 ns) = 4.886 ns; Loc. = LC_X1_Y30_N8; Fanout = 6; REG Node = 'q[0]'
        Info: Total cell delay = 1.692 ns ( 34.63 % )
        Info: Total interconnect delay = 3.194 ns ( 65.37 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Apr 01 20:19:12 2008
    Info: Elapsed time: 00:00:01