count_10.tan.qmsg

来自「数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "ITDB_TSU_RESULT" "q\[3\] en clk 3.231 ns register " "Info: tsu for register \"q\[3\]\" (data pin = \"en\", clock pin = \"clk\") is 3.231 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.155 ns + Longest pin register " "Info: + Longest pin to register delay is 6.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns en 1 PIN PIN_C20 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C20; Fanout = 1; PIN Node = 'en'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.698 ns) + CELL(0.183 ns) 4.968 ns q\[3\]~308 2 COMB LC_X1_Y30_N6 4 " "Info: 2: + IC(3.698 ns) + CELL(0.183 ns) = 4.968 ns; Loc. = LC_X1_Y30_N6; Fanout = 4; COMB Node = 'q\[3\]~308'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.881 ns" { en q[3]~308 } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.705 ns) 6.155 ns q\[3\] 3 REG LC_X1_Y30_N5 4 " "Info: 3: + IC(0.482 ns) + CELL(0.705 ns) = 6.155 ns; Loc. = LC_X1_Y30_N5; Fanout = 4; REG Node = 'q\[3\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.187 ns" { q[3]~308 q[3] } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.975 ns ( 32.09 % ) " "Info: Total cell delay = 1.975 ns ( 32.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.180 ns ( 67.91 % ) " "Info: Total interconnect delay = 4.180 ns ( 67.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.155 ns" { en q[3]~308 q[3] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "6.155 ns" { en en~out0 q[3]~308 q[3] } { 0.000ns 0.000ns 3.698ns 0.482ns } { 0.000ns 1.087ns 0.183ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.934 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns q\[3\] 2 REG LC_X1_Y30_N5 4 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 4; REG Node = 'q\[3\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk q[3] } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk q[3] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 q[3] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.155 ns" { en q[3]~308 q[3] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "6.155 ns" { en en~out0 q[3]~308 q[3] } { 0.000ns 0.000ns 3.698ns 0.482ns } { 0.000ns 1.087ns 0.183ns 0.705ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk q[3] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 q[3] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qc q\[1\] 6.667 ns register " "Info: tco from clock \"clk\" to destination pin \"qc\" through register \"q\[1\]\" is 6.667 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns q\[1\] 2 REG LC_X1_Y30_N3 5 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N3; Fanout = 5; REG Node = 'q\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk q[1] } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk q[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 q[1] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.577 ns + Longest register pin " "Info: + Longest register to pin delay is 3.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[1\] 1 REG LC_X1_Y30_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N3; Fanout = 5; REG Node = 'q\[1\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { q[1] } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(2.404 ns) 3.577 ns qc 2 PIN PIN_B20 0 " "Info: 2: + IC(1.173 ns) + CELL(2.404 ns) = 3.577 ns; Loc. = PIN_B20; Fanout = 0; PIN Node = 'qc'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.577 ns" { q[1] qc } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.21 % ) " "Info: Total cell delay = 2.404 ns ( 67.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.173 ns ( 32.79 % ) " "Info: Total interconnect delay = 1.173 ns ( 32.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.577 ns" { q[1] qc } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "3.577 ns" { q[1] qc } { 0.000ns 1.173ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk q[1] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 q[1] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.577 ns" { q[1] qc } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "3.577 ns" { q[1] qc } { 0.000ns 1.173ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q\[0\] clr clk -1.852 ns register " "Info: th for register \"q\[0\]\" (data pin = \"clr\", clock pin = \"clk\") is -1.852 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns q\[0\] 2 REG LC_X1_Y30_N8 6 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 6; REG Node = 'q\[0\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk q[0] } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk q[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.886 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.886 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns clr 1 PIN PIN_D21 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_D21; Fanout = 3; PIN Node = 'clr'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.194 ns) + CELL(0.458 ns) 4.886 ns q\[0\] 2 REG LC_X1_Y30_N8 6 " "Info: 2: + IC(3.194 ns) + CELL(0.458 ns) = 4.886 ns; Loc. = LC_X1_Y30_N8; Fanout = 6; REG Node = 'q\[0\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.652 ns" { clr q[0] } "NODE_NAME" } } { "count_10.vhd" "" { Text "D:/Quartus II/count_10/count_10.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.692 ns ( 34.63 % ) " "Info: Total cell delay = 1.692 ns ( 34.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.194 ns ( 65.37 % ) " "Info: Total interconnect delay = 3.194 ns ( 65.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.886 ns" { clr q[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.886 ns" { clr clr~out0 q[0] } { 0.000ns 0.000ns 3.194ns } { 0.000ns 1.234ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk q[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.886 ns" { clr q[0] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.886 ns" { clr clr~out0 q[0] } { 0.000ns 0.000ns 3.194ns } { 0.000ns 1.234ns 0.458ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 01 20:19:12 2008 " "Info: Processing ended: Tue Apr 01 20:19:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}