count_10.sim.rpt

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

; |count_10|q~10                                                           ; |count_10|q~10                                                                ; out              ;
; |count_10|q~11                                                           ; |count_10|q~11                                                                ; out              ;
; |count_10|q[0]                                                           ; |count_10|q[0]                                                                ; out              ;
; |count_10|q[1]                                                           ; |count_10|q[1]                                                                ; out              ;
; |count_10|q[2]                                                           ; |count_10|q[2]                                                                ; out              ;
; |count_10|q[3]                                                           ; |count_10|q[3]                                                                ; out              ;
; |count_10|clk                                                            ; |count_10|clk                                                                 ; out              ;
; |count_10|qa                                                             ; |count_10|qa                                                                  ; pin_out          ;
; |count_10|qb                                                             ; |count_10|qb                                                                  ; pin_out          ;
; |count_10|qc                                                             ; |count_10|qc                                                                  ; pin_out          ;
; |count_10|qd                                                             ; |count_10|qd                                                                  ; pin_out          ;
; |count_10|LessThan0~16                                                   ; |count_10|LessThan0~16                                                        ; out0             ;
; |count_10|LessThan0~17                                                   ; |count_10|LessThan0~17                                                        ; out0             ;
; |count_10|LessThan0~18                                                   ; |count_10|LessThan0~18                                                        ; out0             ;
; |count_10|LessThan0~19                                                   ; |count_10|LessThan0~19                                                        ; out0             ;
; |count_10|lpm_add_sub:Add0|result_node[0]                                ; |count_10|lpm_add_sub:Add0|result_node[0]                                     ; out0             ;
; |count_10|lpm_add_sub:Add0|result_node[1]                                ; |count_10|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |count_10|lpm_add_sub:Add0|result_node[2]                                ; |count_10|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |count_10|lpm_add_sub:Add0|result_node[3]                                ; |count_10|lpm_add_sub:Add0|result_node[3]                                     ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~0                             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~0                                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~3                             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~3                                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1             ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2             ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3             ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]               ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                    ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]               ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]               ; |count_10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~7                             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~7                                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~8                             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~8                                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~9                             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~9                                  ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~10                            ; |count_10|lpm_add_sub:Add0|addcore:adder|_~10                                 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~11                            ; |count_10|lpm_add_sub:Add0|addcore:adder|_~11                                 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~12                            ; |count_10|lpm_add_sub:Add0|addcore:adder|_~12                                 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~13                            ; |count_10|lpm_add_sub:Add0|addcore:adder|_~13                                 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~14                            ; |count_10|lpm_add_sub:Add0|addcore:adder|_~14                                 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~15                            ; |count_10|lpm_add_sub:Add0|addcore:adder|_~15                                 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |count_10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                               ;
+----------------------------------------------------------+----------------------------------------------------------+------------------+
; Node Name                                                ; Output Port Name                                         ; Output Port Type ;
+----------------------------------------------------------+----------------------------------------------------------+------------------+
; |count_10|clr                                            ; |count_10|clr                                            ; out              ;
; |count_10|en                                             ; |count_10|en                                             ; out              ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~1             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~1             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~2             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~2             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~4             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~4             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~5             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~5             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~6             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~6             ; out0             ;
+----------------------------------------------------------+----------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                               ;
+----------------------------------------------------------+----------------------------------------------------------+------------------+
; Node Name                                                ; Output Port Name                                         ; Output Port Type ;
+----------------------------------------------------------+----------------------------------------------------------+------------------+
; |count_10|clr                                            ; |count_10|clr                                            ; out              ;
; |count_10|en                                             ; |count_10|en                                             ; out              ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~1             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~1             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~2             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~2             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; |count_10|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~4             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~4             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~5             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~5             ; out0             ;
; |count_10|lpm_add_sub:Add0|addcore:adder|_~6             ; |count_10|lpm_add_sub:Add0|addcore:adder|_~6             ; out0             ;
+----------------------------------------------------------+----------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Apr 03 23:50:12 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off count_10 -c count_10
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      80.88 %
Info: Number of transitions in simulation is 4399
Info: Vector file count_10.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Apr 03 23:50:13 2008
    Info: Elapsed time: 00:00:01