mux2to1.tan.qmsg

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "s1 register register inst3 inst3 450.05 MHz Internal " "Info: Clock \"s1\" Internal fmax is restricted to 450.05 MHz between source register \"inst3\" and destination register \"inst3\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Longest register register " "Info: + Longest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X29_Y35_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns inst3~2 2 COMB LCCOMB_X29_Y35_N20 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 1; COMB Node = 'inst3~2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.323 ns" { inst3 inst3~2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns inst3 3 REG LCFF_X29_Y35_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { inst3~2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { inst3 inst3~2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.407 ns" { inst3 inst3~2 inst3 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s1 destination 5.138 ns + Shortest register " "Info: + Shortest clock path from clock \"s1\" to destination register is 5.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns s1 1 CLK PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 's1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { s1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 64 128 296 80 "s1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.271 ns) 2.074 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.963 ns) + CELL(0.271 ns) = 2.074 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.234 ns" { s1 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 3.087 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.087 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.309 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.309 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 5.138 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.138 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.222 ns ( 62.71 % ) " "Info: Total cell delay = 3.222 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.916 ns ( 37.29 % ) " "Info: Total interconnect delay = 1.916 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s1 source 5.138 ns - Longest register " "Info: - Longest clock path from clock \"s1\" to source register is 5.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns s1 1 CLK PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 's1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { s1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 64 128 296 80 "s1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.271 ns) 2.074 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.963 ns) + CELL(0.271 ns) = 2.074 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.234 ns" { s1 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 3.087 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.087 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.309 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.309 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 5.138 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.138 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.222 ns ( 62.71 % ) " "Info: Total cell delay = 3.222 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.916 ns ( 37.29 % ) " "Info: Total interconnect delay = 1.916 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { inst3 inst3~2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.407 ns" { inst3 inst3~2 inst3 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "" { inst3 } {  } {  } } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "w0 register register inst3 inst3 420.17 MHz Internal " "Info: Clock \"w0\" Internal fmax is restricted to 420.17 MHz between source register \"inst3\" and destination register \"inst3\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Longest register register " "Info: + Longest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X29_Y35_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns inst3~2 2 COMB LCCOMB_X29_Y35_N20 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 1; COMB Node = 'inst3~2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.323 ns" { inst3 inst3~2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns inst3 3 REG LCFF_X29_Y35_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { inst3~2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { inst3 inst3~2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.407 ns" { inst3 inst3~2 inst3 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "w0 destination 5.104 ns + Shortest register " "Info: + Shortest clock path from clock \"w0\" to destination register is 5.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns w0 1 CLK PIN_D13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'w0'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { w0 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 8 128 296 24 "w0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.641 ns) + CELL(0.420 ns) 2.040 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.641 ns) + CELL(0.420 ns) = 2.040 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.061 ns" { w0 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 3.053 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.053 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.275 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.275 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 5.104 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.104 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.510 ns ( 68.77 % ) " "Info: Total cell delay = 3.510 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.594 ns ( 31.23 % ) " "Info: Total interconnect delay = 1.594 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.104 ns" { w0 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.104 ns" { w0 w0~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.641ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.420ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "w0 source 5.104 ns - Longest register " "Info: - Longest clock path from clock \"w0\" to source register is 5.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns w0 1 CLK PIN_D13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'w0'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { w0 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 8 128 296 24 "w0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.641 ns) + CELL(0.420 ns) 2.040 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.641 ns) + CELL(0.420 ns) = 2.040 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.061 ns" { w0 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 3.053 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.053 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.275 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.275 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 5.104 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.104 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.510 ns ( 68.77 % ) " "Info: Total cell delay = 3.510 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.594 ns ( 31.23 % ) " "Info: Total interconnect delay = 1.594 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.104 ns" { w0 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.104 ns" { w0 w0~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.641ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.420ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.104 ns" { w0 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.104 ns" { w0 w0~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.641ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.420ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.104 ns" { w0 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.104 ns" { w0 w0~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.641ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.420ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { inst3 inst3~2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.407 ns" { inst3 inst3~2 inst3 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.104 ns" { w0 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.104 ns" { w0 w0~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.641ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.420ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.104 ns" { w0 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.104 ns" { w0 w0~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.641ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.420ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "" { inst3 } {  } {  } } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "s1 out\[3\] inst3 8.841 ns register " "Info: tco from clock \"s1\" to destination pin \"out\[3\]\" through register \"inst3\" is 8.841 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s1 source 5.138 ns + Longest register " "Info: + Longest clock path from clock \"s1\" to source register is 5.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns s1 1 CLK PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 's1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { s1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 64 128 296 80 "s1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.271 ns) 2.074 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.963 ns) + CELL(0.271 ns) = 2.074 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.234 ns" { s1 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 3.087 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.087 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.309 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.309 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 5.138 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.138 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.222 ns ( 62.71 % ) " "Info: Total cell delay = 3.222 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.916 ns ( 37.29 % ) " "Info: Total interconnect delay = 1.916 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.453 ns + Longest register pin " "Info: + Longest register to pin delay is 3.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X29_Y35_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.625 ns) + CELL(2.828 ns) 3.453 ns out\[3\] 2 PIN PIN_J10 0 " "Info: 2: + IC(0.625 ns) + CELL(2.828 ns) = 3.453 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'out\[3\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.453 ns" { inst3 out[3] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 24 584 760 40 "out\[3..1\]" "" } { 16 552 593 32 "out\[3..1\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.828 ns ( 81.90 % ) " "Info: Total cell delay = 2.828 ns ( 81.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.625 ns ( 18.10 % ) " "Info: Total interconnect delay = 0.625 ns ( 18.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.453 ns" { inst3 out[3] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "3.453 ns" { inst3 out[3] } { 0.000ns 0.625ns } { 0.000ns 2.828ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.138 ns" { s1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "5.138 ns" { s1 s1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.963ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.840ns 0.271ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.453 ns" { inst3 out[3] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "3.453 ns" { inst3 out[3] } { 0.000ns 0.625ns } { 0.000ns 2.828ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}