mux2to1.tan.qmsg

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "w1 " "Info: Assuming node \"w1\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 32 128 296 48 "w1" "" } } } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "w1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "s1 " "Info: Assuming node \"s1\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 64 128 296 80 "s1" "" } } } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "s1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "w0 " "Info: Assuming node \"w0\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 8 128 296 24 "w0" "" } } } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "w0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "mux2to1:inst\|f~8 " "Info: Detected gated clock \"mux2to1:inst\|f~8\" as buffer" {  } { { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "mux2to1:inst\|f~8" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inst1 " "Info: Detected ripple clock \"inst1\" as buffer" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "inst1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inst2 " "Info: Detected ripple clock \"inst2\" as buffer" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } } { "d:/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "inst2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "w1 register register inst3 inst3 420.17 MHz Internal " "Info: Clock \"w1\" Internal fmax is restricted to 420.17 MHz between source register \"inst3\" and destination register \"inst3\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Longest register register " "Info: + Longest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X29_Y35_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns inst3~2 2 COMB LCCOMB_X29_Y35_N20 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 1; COMB Node = 'inst3~2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.323 ns" { inst3 inst3~2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns inst3 3 REG LCFF_X29_Y35_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { inst3~2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { inst3 inst3~2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.407 ns" { inst3 inst3~2 inst3 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "w1 destination 4.830 ns + Shortest register " "Info: + Shortest clock path from clock \"w1\" to destination register is 4.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns w1 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'w1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { w1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 32 128 296 48 "w1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.150 ns) 1.766 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.637 ns) + CELL(0.150 ns) = 1.766 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.787 ns" { w1 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 2.779 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 2.779 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.001 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.001 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 4.830 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 4.830 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.240 ns ( 67.08 % ) " "Info: Total cell delay = 3.240 ns ( 67.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.590 ns ( 32.92 % ) " "Info: Total interconnect delay = 1.590 ns ( 32.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.830 ns" { w1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.830 ns" { w1 w1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.637ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.150ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "w1 source 4.830 ns - Longest register " "Info: - Longest clock path from clock \"w1\" to source register is 4.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns w1 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'w1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { w1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 32 128 296 48 "w1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.150 ns) 1.766 ns mux2to1:inst\|f~8 2 COMB LCCOMB_X30_Y35_N2 1 " "Info: 2: + IC(0.637 ns) + CELL(0.150 ns) = 1.766 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst\|f~8'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.787 ns" { w1 mux2to1:inst|f~8 } "NODE_NAME" } } { "mux2to1.vhd" "" { Text "D:/Quartus II/mux2to1/mux2to1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.226 ns) + CELL(0.787 ns) 2.779 ns inst1 3 REG LCFF_X30_Y35_N15 3 " "Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 2.779 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.013 ns" { mux2to1:inst|f~8 inst1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 288 352 216 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.787 ns) 4.001 ns inst2 4 REG LCFF_X29_Y35_N1 3 " "Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.001 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.222 ns" { inst1 inst2 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 448 512 216 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.537 ns) 4.830 ns inst3 5 REG LCFF_X29_Y35_N21 2 " "Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 4.830 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.829 ns" { inst2 inst3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.240 ns ( 67.08 % ) " "Info: Total cell delay = 3.240 ns ( 67.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.590 ns ( 32.92 % ) " "Info: Total interconnect delay = 1.590 ns ( 32.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.830 ns" { w1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.830 ns" { w1 w1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.637ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.150ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.830 ns" { w1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.830 ns" { w1 w1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.637ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.150ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.830 ns" { w1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.830 ns" { w1 w1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.637ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.150ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { inst3 inst3~2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "0.407 ns" { inst3 inst3~2 inst3 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.830 ns" { w1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.830 ns" { w1 w1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.637ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.150ns 0.787ns 0.787ns 0.537ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "4.830 ns" { w1 mux2to1:inst|f~8 inst1 inst2 inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "4.830 ns" { w1 w1~combout mux2to1:inst|f~8 inst1 inst2 inst3 } { 0.000ns 0.000ns 0.637ns 0.226ns 0.435ns 0.292ns } { 0.000ns 0.979ns 0.150ns 0.787ns 0.787ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "" { inst3 } {  } {  } } } { "Block1.bdf" "" { Schematic "D:/Quartus II/mux2to1/Block1.bdf" { { 136 592 656 216 "inst3" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}