mux2to1.tan.rpt

数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码

; N/A   ; None         ; 8.841 ns   ; inst3 ; out[3] ; s1         ;
; N/A   ; None         ; 8.807 ns   ; inst3 ; out[3] ; w0         ;
; N/A   ; None         ; 8.533 ns   ; inst3 ; out[3] ; w1         ;
; N/A   ; None         ; 7.759 ns   ; inst2 ; out[2] ; s1         ;
; N/A   ; None         ; 7.725 ns   ; inst2 ; out[2] ; w0         ;
; N/A   ; None         ; 7.451 ns   ; inst2 ; out[2] ; w1         ;
; N/A   ; None         ; 6.517 ns   ; inst1 ; out[1] ; s1         ;
; N/A   ; None         ; 6.483 ns   ; inst1 ; out[1] ; w0         ;
; N/A   ; None         ; 6.209 ns   ; inst1 ; out[1] ; w1         ;
+-------+--------------+------------+-------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Mar 26 16:36:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux2to1 -c mux2to1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "w1" is an undefined clock
    Info: Assuming node "s1" is an undefined clock
    Info: Assuming node "w0" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "mux2to1:inst|f~8" as buffer
    Info: Detected ripple clock "inst1" as buffer
    Info: Detected ripple clock "inst2" as buffer
Info: Clock "w1" Internal fmax is restricted to 420.17 MHz between source register "inst3" and destination register "inst3"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.407 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 1; COMB Node = 'inst3~2'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
            Info: Total cell delay = 0.407 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "w1" to destination register is 4.830 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'w1'
                Info: 2: + IC(0.637 ns) + CELL(0.150 ns) = 1.766 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
                Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 2.779 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
                Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.001 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
                Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 4.830 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
                Info: Total cell delay = 3.240 ns ( 67.08 % )
                Info: Total interconnect delay = 1.590 ns ( 32.92 % )
            Info: - Longest clock path from clock "w1" to source register is 4.830 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'w1'
                Info: 2: + IC(0.637 ns) + CELL(0.150 ns) = 1.766 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
                Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 2.779 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
                Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.001 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
                Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 4.830 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
                Info: Total cell delay = 3.240 ns ( 67.08 % )
                Info: Total interconnect delay = 1.590 ns ( 32.92 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "s1" Internal fmax is restricted to 450.05 MHz between source register "inst3" and destination register "inst3"
    Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.407 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 1; COMB Node = 'inst3~2'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
            Info: Total cell delay = 0.407 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "s1" to destination register is 5.138 ns
                Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 's1'
                Info: 2: + IC(0.963 ns) + CELL(0.271 ns) = 2.074 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
                Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.087 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
                Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.309 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
                Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.138 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
                Info: Total cell delay = 3.222 ns ( 62.71 % )
                Info: Total interconnect delay = 1.916 ns ( 37.29 % )
            Info: - Longest clock path from clock "s1" to source register is 5.138 ns
                Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 's1'
                Info: 2: + IC(0.963 ns) + CELL(0.271 ns) = 2.074 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
                Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.087 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
                Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.309 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
                Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.138 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
                Info: Total cell delay = 3.222 ns ( 62.71 % )
                Info: Total interconnect delay = 1.916 ns ( 37.29 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "w0" Internal fmax is restricted to 420.17 MHz between source register "inst3" and destination register "inst3"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.407 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 1; COMB Node = 'inst3~2'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
            Info: Total cell delay = 0.407 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "w0" to destination register is 5.104 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'w0'
                Info: 2: + IC(0.641 ns) + CELL(0.420 ns) = 2.040 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
                Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.053 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
                Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.275 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
                Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.104 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
                Info: Total cell delay = 3.510 ns ( 68.77 % )
                Info: Total interconnect delay = 1.594 ns ( 31.23 % )
            Info: - Longest clock path from clock "w0" to source register is 5.104 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'w0'
                Info: 2: + IC(0.641 ns) + CELL(0.420 ns) = 2.040 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
                Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.053 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
                Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.275 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
                Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.104 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
                Info: Total cell delay = 3.510 ns ( 68.77 % )
                Info: Total interconnect delay = 1.594 ns ( 31.23 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "s1" to destination pin "out[3]" through register "inst3" is 8.841 ns
    Info: + Longest clock path from clock "s1" to source register is 5.138 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 's1'
        Info: 2: + IC(0.963 ns) + CELL(0.271 ns) = 2.074 ns; Loc. = LCCOMB_X30_Y35_N2; Fanout = 1; COMB Node = 'mux2to1:inst|f~8'
        Info: 3: + IC(0.226 ns) + CELL(0.787 ns) = 3.087 ns; Loc. = LCFF_X30_Y35_N15; Fanout = 3; REG Node = 'inst1'
        Info: 4: + IC(0.435 ns) + CELL(0.787 ns) = 4.309 ns; Loc. = LCFF_X29_Y35_N1; Fanout = 3; REG Node = 'inst2'
        Info: 5: + IC(0.292 ns) + CELL(0.537 ns) = 5.138 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
        Info: Total cell delay = 3.222 ns ( 62.71 % )
        Info: Total interconnect delay = 1.916 ns ( 37.29 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.453 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N21; Fanout = 2; REG Node = 'inst3'
        Info: 2: + IC(0.625 ns) + CELL(2.828 ns) = 3.453 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'out[3]'
        Info: Total cell delay = 2.828 ns ( 81.90 % )
        Info: Total interconnect delay = 0.625 ns ( 18.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Mar 26 16:36:14 2008
    Info: Elapsed time: 00:00:01