mux2to1.vhd

来自「数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all;

entity   mux2to1 is
port(
		w0,w1,s:in std_logic;
		f		:out std_logic);
end mux2to1;

architecture    behavior of  mux2to1 is
	begin 
	f<=w0 when s='0' else w1;
end behavior;