osc_control.v

来自「verilog编写基于FPGA的示波器核心实现」· Verilog 代码 · 共 70 行

module osc_control(
					oscaddrin,
					oscdatain,
					osc_sig,
					cs,
					clk,
					ADDROUT,
					DATAOUT,
					rden,
					wren
					);
input [16:0] oscaddrin;					
input [15:0] oscdatain;
input osc_sig;
input cs;
input clk;
output reg [9:0] ADDROUT;
output reg [7:0]  DATAOUT;
output reg rden;
output reg wren;


parameter 	IDLE		=	4'b0001,
			ALLIN		=	4'b0010,
			WAIT1		=	4'b0100,
			WAIT2		=	4'b1000;

reg [3:0] state;

always @(posedge clk)                                                                        
begin
if (cs)
	begin
	wren<=0;
	rden<=1;
	state<=IDLE;
	end
else
	case (state)
	default	:begin					//IDLE
			wren<=0;
			rden<=1;
			if (osc_sig)
				begin
				state<=ALLIN;
				end
			else
				state<=IDLE;	
			end	
	ALLIN:	begin
			ADDROUT<={oscaddrin[13:8],oscaddrin[3:0]};
			DATAOUT<=oscdatain[7:0];
			state<=WAIT1;
			wren<=0;
			rden<=0;
			end
	WAIT1:	begin
			wren<=1;
			rden<=0;
			state<=WAIT2;
			end	
	WAIT2:	begin
			wren<=1;
			rden<=0;
			state<=IDLE;
			end															
	endcase
end	

endmodule