phase_test.sim.rpt

verilog编写基于fpga的鉴相器模块

Simulator report for phase_test
Sun Aug 19 21:02:58 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Coverage Summary
  6. Complete 1/0-Value Coverage
  7. Missing 1-Value Coverage
  8. Missing 0-Value Coverage
  9. Simulator INI Usage
 10. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 200.0 us     ;
; Simulation Netlist Size     ; 173 nodes    ;
; Simulation Coverage         ;      20.59 % ;
; Total Number of Transitions ; 33364        ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone      ;
; Device                      ; EP1C6Q240C8  ;
+-----------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                          ;
+--------------------------------------------------------------------------------------------+----------------+---------------+
; Option                                                                                     ; Setting        ; Default Value ;
+--------------------------------------------------------------------------------------------+----------------+---------------+
; Simulation mode                                                                            ; Timing         ; Timing        ;
; Start time                                                                                 ; 0 ns           ; 0 ns          ;
; Vector input source                                                                        ; phase_test.vwf ;               ;
; Add pins automatically to simulation output waveforms                                      ; On             ; On            ;
; Check outputs                                                                              ; Off            ; Off           ;
; Report simulation coverage                                                                 ; On             ; On            ;
; Display complete 1/0 value coverage report                                                 ; On             ; On            ;
; Display missing 1-value coverage report                                                    ; On             ; On            ;