wed.zsf

verilog编写fpga与片外SRAM通信模块

F:/fpga test/sram_control/db/sram_control.sim.vwf	3656	368424	748	364768	4
F:/fpga test/sram_control/sram_control.vwf	307625	807625	859	500000	59
F:/fpga test/sram_control/Waveform1.vwf	162900	334700	859	171800	0
sram_control.vwf	80400	424000	859	343600	23
Waveform1.vwf	30375	64125	0	0	0