📄 sram_control.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counttemp\[3\] register state.RD_ADDRNEW 140.37 MHz 7.124 ns Internal " "Info: Clock \"clk\" has Internal fmax of 140.37 MHz between source register \"counttemp\[3\]\" and destination register \"state.RD_ADDRNEW\" (period= 7.124 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.863 ns + Longest register register " "Info: + Longest register to register delay is 6.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counttemp\[3\] 1 REG LC_X25_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y10_N5; Fanout = 4; REG Node = 'counttemp\[3\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counttemp[3] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.114 ns) 1.418 ns Equal0~201 2 COMB LC_X24_Y9_N2 1 " "Info: 2: + IC(1.304 ns) + CELL(0.114 ns) = 1.418 ns; Loc. = LC_X24_Y9_N2; Fanout = 1; COMB Node = 'Equal0~201'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.418 ns" { counttemp[3] Equal0~201 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.590 ns) 3.245 ns Equal0~204 3 COMB LC_X24_Y10_N7 1 " "Info: 3: + IC(1.237 ns) + CELL(0.590 ns) = 3.245 ns; Loc. = LC_X24_Y10_N7; Fanout = 1; COMB Node = 'Equal0~204'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.827 ns" { Equal0~201 Equal0~204 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.541 ns Equal0~205 4 COMB LC_X24_Y10_N8 10 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.541 ns; Loc. = LC_X24_Y10_N8; Fanout = 10; COMB Node = 'Equal0~205'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal0~204 Equal0~205 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.114 ns) 4.873 ns Selector58~29 5 COMB LC_X27_Y10_N6 1 " "Info: 5: + IC(1.218 ns) + CELL(0.114 ns) = 4.873 ns; Loc. = LC_X27_Y10_N6; Fanout = 1; COMB Node = 'Selector58~29'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.332 ns" { Equal0~205 Selector58~29 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 90 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.309 ns) 6.863 ns state.RD_ADDRNEW 6 REG LC_X25_Y11_N0 10 " "Info: 6: + IC(1.681 ns) + CELL(0.309 ns) = 6.863 ns; Loc. = LC_X25_Y11_N0; Fanout = 10; REG Node = 'state.RD_ADDRNEW'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.990 ns" { Selector58~29 state.RD_ADDRNEW } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.241 ns ( 18.08 % ) " "Info: Total cell delay = 1.241 ns ( 18.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.622 ns ( 81.92 % ) " "Info: Total interconnect delay = 5.622 ns ( 81.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.863 ns" { counttemp[3] Equal0~201 Equal0~204 Equal0~205 Selector58~29 state.RD_ADDRNEW } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.863 ns" { counttemp[3] Equal0~201 Equal0~204 Equal0~205 Selector58~29 state.RD_ADDRNEW } { 0.000ns 1.304ns 1.237ns 0.182ns 1.218ns 1.681ns } { 0.000ns 0.114ns 0.590ns 0.114ns 0.114ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns state.RD_ADDRNEW 2 REG LC_X25_Y11_N0 10 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X25_Y11_N0; Fanout = 10; REG Node = 'state.RD_ADDRNEW'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk state.RD_ADDRNEW } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk state.RD_ADDRNEW } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 state.RD_ADDRNEW } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns counttemp\[3\] 2 REG LC_X25_Y10_N5 4 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X25_Y10_N5; Fanout = 4; REG Node = 'counttemp\[3\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk counttemp[3] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk counttemp[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 counttemp[3] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk state.RD_ADDRNEW } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 state.RD_ADDRNEW } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk counttemp[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 counttemp[3] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 55 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.863 ns" { counttemp[3] Equal0~201 Equal0~204 Equal0~205 Selector58~29 state.RD_ADDRNEW } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.863 ns" { counttemp[3] Equal0~201 Equal0~204 Equal0~205 Selector58~29 state.RD_ADDRNEW } { 0.000ns 1.304ns 1.237ns 0.182ns 1.218ns 1.681ns } { 0.000ns 0.114ns 0.590ns 0.114ns 0.114ns 0.309ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk state.RD_ADDRNEW } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 state.RD_ADDRNEW } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk counttemp[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 counttemp[3] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "addrbuf\[13\] rd_busy_sig clk 10.494 ns register " "Info: tsu for register \"addrbuf\[13\]\" (data pin = \"rd_busy_sig\", clock pin = \"clk\") is 10.494 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.627 ns + Longest pin register " "Info: + Longest pin to register delay is 13.627 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rd_busy_sig 1 PIN PIN_141 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_141; Fanout = 7; PIN Node = 'rd_busy_sig'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_busy_sig } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.269 ns) + CELL(0.590 ns) 10.328 ns addrbuf\[16\]~1044 2 COMB LC_X23_Y10_N1 1 " "Info: 2: + IC(8.269 ns) + CELL(0.590 ns) = 10.328 ns; Loc. = LC_X23_Y10_N1; Fanout = 1; COMB Node = 'addrbuf\[16\]~1044'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.859 ns" { rd_busy_sig addrbuf[16]~1044 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.590 ns) 11.353 ns addrbuf\[16\]~1045 3 COMB LC_X23_Y10_N0 3 " "Info: 3: + IC(0.435 ns) + CELL(0.590 ns) = 11.353 ns; Loc. = LC_X23_Y10_N0; Fanout = 3; COMB Node = 'addrbuf\[16\]~1045'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.025 ns" { addrbuf[16]~1044 addrbuf[16]~1045 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.423 ns) 12.188 ns addrbuf\[0\]~1026 4 COMB LC_X23_Y10_N2 2 " "Info: 4: + IC(0.412 ns) + CELL(0.423 ns) = 12.188 ns; Loc. = LC_X23_Y10_N2; Fanout = 2; COMB Node = 'addrbuf\[0\]~1026'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.835 ns" { addrbuf[16]~1045 addrbuf[0]~1026 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 12.266 ns addrbuf\[1\]~1027 5 COMB LC_X23_Y10_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 12.266 ns; Loc. = LC_X23_Y10_N3; Fanout = 2; COMB Node = 'addrbuf\[1\]~1027'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { addrbuf[0]~1026 addrbuf[1]~1027 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 12.444 ns addrbuf\[2\]~1028 6 COMB LC_X23_Y10_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 12.444 ns; Loc. = LC_X23_Y10_N4; Fanout = 6; COMB Node = 'addrbuf\[2\]~1028'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { addrbuf[1]~1027 addrbuf[2]~1028 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 12.652 ns addrbuf\[7\]~1033 7 COMB LC_X23_Y10_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 12.652 ns; Loc. = LC_X23_Y10_N9; Fanout = 6; COMB Node = 'addrbuf\[7\]~1033'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { addrbuf[2]~1028 addrbuf[7]~1033 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 12.788 ns addrbuf\[12\]~1038 8 COMB LC_X23_Y9_N4 4 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 12.788 ns; Loc. = LC_X23_Y9_N4; Fanout = 4; COMB Node = 'addrbuf\[12\]~1038'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { addrbuf[7]~1033 addrbuf[12]~1038 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 13.627 ns addrbuf\[13\] 9 REG LC_X23_Y9_N5 4 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 13.627 ns; Loc. = LC_X23_Y9_N5; Fanout = 4; REG Node = 'addrbuf\[13\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { addrbuf[12]~1038 addrbuf[13] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.511 ns ( 33.10 % ) " "Info: Total cell delay = 4.511 ns ( 33.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.116 ns ( 66.90 % ) " "Info: Total interconnect delay = 9.116 ns ( 66.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.627 ns" { rd_busy_sig addrbuf[16]~1044 addrbuf[16]~1045 addrbuf[0]~1026 addrbuf[1]~1027 addrbuf[2]~1028 addrbuf[7]~1033 addrbuf[12]~1038 addrbuf[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "13.627 ns" { rd_busy_sig rd_busy_sig~out0 addrbuf[16]~1044 addrbuf[16]~1045 addrbuf[0]~1026 addrbuf[1]~1027 addrbuf[2]~1028 addrbuf[7]~1033 addrbuf[12]~1038 addrbuf[13] } { 0.000ns 0.000ns 8.269ns 0.435ns 0.412ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns addrbuf\[13\] 2 REG LC_X23_Y9_N5 4 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X23_Y9_N5; Fanout = 4; REG Node = 'addrbuf\[13\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk addrbuf[13] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk addrbuf[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 addrbuf[13] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.627 ns" { rd_busy_sig addrbuf[16]~1044 addrbuf[16]~1045 addrbuf[0]~1026 addrbuf[1]~1027 addrbuf[2]~1028 addrbuf[7]~1033 addrbuf[12]~1038 addrbuf[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "13.627 ns" { rd_busy_sig rd_busy_sig~out0 addrbuf[16]~1044 addrbuf[16]~1045 addrbuf[0]~1026 addrbuf[1]~1027 addrbuf[2]~1028 addrbuf[7]~1033 addrbuf[12]~1038 addrbuf[13] } { 0.000ns 0.000ns 8.269ns 0.435ns 0.412ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk addrbuf[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 addrbuf[13] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk DATA\[11\] link_wr 12.971 ns register " "Info: tco from clock \"clk\" to destination pin \"DATA\[11\]\" through register \"link_wr\" is 12.971 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns link_wr 2 REG LC_X24_Y12_N9 17 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X24_Y12_N9; Fanout = 17; REG Node = 'link_wr'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk link_wr } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk link_wr } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 link_wr } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 46 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.577 ns + Longest register pin " "Info: + Longest register to pin delay is 9.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns link_wr 1 REG LC_X24_Y12_N9 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y12_N9; Fanout = 17; REG Node = 'link_wr'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { link_wr } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.498 ns) + CELL(2.079 ns) 9.577 ns DATA\[11\] 2 PIN PIN_197 0 " "Info: 2: + IC(7.498 ns) + CELL(2.079 ns) = 9.577 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'DATA\[11\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.577 ns" { link_wr DATA[11] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.079 ns ( 21.71 % ) " "Info: Total cell delay = 2.079 ns ( 21.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.498 ns ( 78.29 % ) " "Info: Total interconnect delay = 7.498 ns ( 78.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.577 ns" { link_wr DATA[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "9.577 ns" { link_wr DATA[11] } { 0.000ns 7.498ns } { 0.000ns 2.079ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk link_wr } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 link_wr } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.577 ns" { link_wr DATA[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "9.577 ns" { link_wr DATA[11] } { 0.000ns 7.498ns } { 0.000ns 2.079ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "DATA\[13\] databus\[13\] 9.475 ns Longest " "Info: Longest tpd from source pin \"DATA\[13\]\" to destination pin \"databus\[13\]\" is 9.475 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[13\] 1 PIN PIN_185 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_185; Fanout = 1; PIN Node = 'DATA\[13\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA[13] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns DATA\[13\]~2 2 COMB IOC_X50_Y27_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X50_Y27_N2; Fanout = 1; COMB Node = 'DATA\[13\]~2'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.475 ns" { DATA[13] DATA[13]~2 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.892 ns) + CELL(2.108 ns) 9.475 ns databus\[13\] 3 PIN PIN_183 0 " "Info: 3: + IC(5.892 ns) + CELL(2.108 ns) = 9.475 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'databus\[13\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { DATA[13]~2 databus[13] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.583 ns ( 37.82 % ) " "Info: Total cell delay = 3.583 ns ( 37.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.892 ns ( 62.18 % ) " "Info: Total interconnect delay = 5.892 ns ( 62.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.475 ns" { DATA[13] DATA[13]~2 databus[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "9.475 ns" { DATA[13] DATA[13]~2 databus[13] } { 0.000ns 0.000ns 5.892ns } { 0.000ns 1.475ns 2.108ns } } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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