sram_control.v

verilog编写fpga与片外SRAM通信模块

module sram_control(
					databus,
					addrbus,
					countbus,
					wr_sig,
					rd_sig,
					wr_busy_sig,  
					rd_busy_sig,
					ad_busy_sig,
					clk,                
					DATA,
					ADDR,
					CE,
					OE,
					WE,
					//UB,
					//LB,
					//ACK,               
					CS				
					);
inout [15:0] databus;				
input [16:0] addrbus;
input [16:0] countbus;
input wr_sig;
input rd_sig;
input wr_busy_sig;
input rd_busy_sig;
input ad_busy_sig;
input clk;
input CS;
inout [15:0] DATA;					
output [16:0] ADDR;
output reg CE;
output reg OE;
output reg WE;
//output UB;
//output LB;
//output reg ACK;

reg [16:0] count_num;
reg [15:0] datawrbuf;
reg [16:0] addrbuf;

reg [16:0] counttemp;           

reg link_wr;
reg link_rd;
reg link_addr;

reg WF;
reg RF;

reg rdfirst;

reg [5:0] state;

parameter IDLE          =	7'b000_001,
		  READY			=	7'b000_010,
		  WR_DATANEW	=	7'b000_100,
		  WR_ADDRNEW	=	7'b001_000,
		  RD_DATANEW	=	7'b010_000,
		  RD_ADDRNEW	=   7'b100_000;

parameter YES = 1'b1,
		  NO  = 1'b0;
		
assign DATA    = link_wr   ?  datawrbuf : 16'bz;
assign ADDR    = link_addr ?  addrbuf   : 16'bz;
assign databus = link_rd   ?  DATA 		: 16'bz;
//assign LB=0;
//assign UB=0;

always @(posedge clk)
if (CS)
		begin
		link_wr<=NO;
		link_rd<=NO;
		link_addr<=NO;
		WF<=0;
		RF<=0;
		datawrbuf<=0;
		addrbuf<=0;
		count_num<=0;
		//ACK<=0;
		CE<=1;OE<=1;WE<=1;
		state<=IDLE;
		end
else 
begin
casex (state)
	 IDLE:  begin
			link_wr<=NO;
			link_rd<=NO;
			link_addr<=NO;
			datawrbuf<=0;
			addrbuf<=0;
		    count_num<=0;
			//ACK<=0;
			CE<=1;OE<=1;WE<=1;
			if (wr_sig)
				begin
				WF<=1;
				RF<=0;
				state<=READY;
				end
			else if (rd_sig)
				begin
				WF<=0;
				RF<=1;
				state<=READY;
				end
			else
				begin
				WF<=0;
				RF<=0;
				state<=IDLE;
				end
			end
	READY:  begin
			count_num<=countbus;         
			counttemp<=17'b1;
			//ACK<=1;
			WE<=1;
			addrbuf<=addrbus;
			link_addr<=YES;			
			if (WF==YES)
				begin
				state<=WR_DATANEW;
				end		
			 if (RF==YES)
				begin
				state<=RD_ADDRNEW;
				rdfirst<=1;
				end
			end
	WR_DATANEW:	begin
				if (wr_busy_sig&&ad_busy_sig)
					begin
					link_wr<=YES;
					WE<=1;				
					state<=WR_DATANEW;
					end
				else
					begin
					link_wr<=YES;
					datawrbuf<=databus;		
					WE<=0;
					CE<=0;
					//ACK<=0;
					state<=WR_ADDRNEW;
					end
				end
	WR_ADDRNEW: begin
				WE<=1;
				//ACK<=1;
				if (counttemp==count_num)
					begin
					state<=IDLE;
					end
				else 
					begin 
					counttemp<=counttemp+17'b1;
					addrbuf<=addrbuf+17'b1;
					state<=WR_DATANEW;
					end
				end
	RD_ADDRNEW: 	begin
	            if(rd_busy_sig)
	               begin
	               state<=RD_ADDRNEW;
	               end
	            else 
	               begin
				   state<=RD_DATANEW;
					if (rdfirst) rdfirst<=0;
				   else addrbuf<=addrbuf+17'b1;
				   OE<=0;
				   CE<=0;
				   end                   
				end
	RD_DATANEW:	begin
				if (counttemp==count_num)
					begin
					if(rd_busy_sig)
						state<=RD_DATANEW;
					else	
						begin
						OE<=1;
						state<=IDLE;
						end
					end
				else 
					begin 
					counttemp<=counttemp+17'b1;					
					state<=RD_ADDRNEW;
					link_rd<=YES;
					end				
				end
	default:	begin		
				state<=IDLE;
				end
	endcase
end 
				
endmodule