sram_control.bdf

verilog编写fpga与片外SRAM通信模块

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "graphic" (version "1.3"))
(symbol
	(rect 272 208 472 400)
	(text "sram_control" (rect 5 0 68 12)(font "Arial" ))
	(text "inst" (rect 8 176 25 188)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "addrbus[16..0]" (rect 0 0 70 12)(font "Arial" ))
		(text "addrbus[16..0]" (rect 21 27 91 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "countbus[16..0]" (rect 0 0 76 12)(font "Arial" ))
		(text "countbus[16..0]" (rect 21 43 97 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 3))
	)
	(port
		(pt 0 64)
		(input)
		(text "wr_sig" (rect 0 0 30 12)(font "Arial" ))
		(text "wr_sig" (rect 21 59 51 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 0 80)
		(input)
		(text "rd_sig" (rect 0 0 29 12)(font "Arial" ))
		(text "rd_sig" (rect 21 75 50 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "busy_sig" (rect 0 0 44 12)(font "Arial" ))
		(text "busy_sig" (rect 21 91 65 103)(font "Arial" ))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 0 112)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 107 35 119)(font "Arial" ))
		(line (pt 0 112)(pt 16 112)(line_width 1))
	)
	(port
		(pt 0 128)
		(input)
		(text "CS" (rect 0 0 15 12)(font "Arial" ))
		(text "CS" (rect 21 123 36 135)(font "Arial" ))
		(line (pt 0 128)(pt 16 128)(line_width 1))
	)
	(port
		(pt 200 64)
		(output)
		(text "ADDR[16..0]" (rect 0 0 63 12)(font "Arial" ))
		(text "ADDR[16..0]" (rect 116 59 179 71)(font "Arial" ))
		(line (pt 200 64)(pt 184 64)(line_width 3))
	)
	(port
		(pt 200 80)
		(output)
		(text "CE" (rect 0 0 15 12)(font "Arial" ))
		(text "CE" (rect 164 75 179 87)(font "Arial" ))
		(line (pt 200 80)(pt 184 80)(line_width 1))
	)
	(port
		(pt 200 96)
		(output)
		(text "OE" (rect 0 0 15 12)(font "Arial" ))
		(text "OE" (rect 164 91 179 103)(font "Arial" ))
		(line (pt 200 96)(pt 184 96)(line_width 1))
	)
	(port
		(pt 200 112)
		(output)
		(text "WE" (rect 0 0 17 12)(font "Arial" ))
		(text "WE" (rect 162 107 179 119)(font "Arial" ))
		(line (pt 200 112)(pt 184 112)(line_width 1))
	)
	(port
		(pt 200 128)
		(output)
		(text "UB" (rect 0 0 15 12)(font "Arial" ))
		(text "UB" (rect 164 123 179 135)(font "Arial" ))
		(line (pt 200 128)(pt 184 128)(line_width 1))
	)
	(port
		(pt 200 144)
		(output)
		(text "LB" (rect 0 0 12 12)(font "Arial" ))
		(text "LB" (rect 167 139 179 151)(font "Arial" ))
		(line (pt 200 144)(pt 184 144)(line_width 1))
	)
	(port
		(pt 200 32)
		(bidir)
		(text "databus[15..0]" (rect 0 0 70 12)(font "Arial" ))
		(text "databus[15..0]" (rect 109 27 179 39)(font "Arial" ))
		(line (pt 200 32)(pt 184 32)(line_width 3))
	)
	(port
		(pt 200 48)
		(bidir)
		(text "DATA[15..0]" (rect 0 0 60 12)(font "Arial" ))
		(text "DATA[15..0]" (rect 119 43 179 55)(font "Arial" ))
		(line (pt 200 48)(pt 184 48)(line_width 3))
	)
	(parameter
		"IDLE"
		"B\"0000001\""
		""
	)
	(parameter
		"READY"
		"B\"0000010\""
		""
	)
	(parameter
		"WR_DATANEW"
		"B\"0000100\""
		""
	)
	(parameter
		"WR_ADDRNEW"
		"B\"0001000\""
		""
	)
	(parameter
		"RD_DATANEW"
		"B\"0010000\""
		""
	)
	(parameter
		"RD_ADDRNEW"
		"B\"0100000\""
		""
	)
	(parameter
		"YES"
		"1"
		""
	)
	(parameter
		"NO"
		"0"
		""
	)
	(drawing
		(rectangle (rect 16 16 184 176)(line_width 1))
	)
	(annotation_block (parameter)(rect 472 80 616 208))
)