sram_control.tan.summary

来自「verilog编写fpga与片外SRAM通信模块」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.494 ns
From           : rd_busy_sig
To             : addrbuf[16]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.971 ns
From           : link_wr
To             : DATA[11]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.475 ns
From           : DATA[13]
To             : databus[13]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.463 ns
From           : addrbus[16]
To             : addrbuf[16]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 140.37 MHz ( period = 7.124 ns )
From           : counttemp[3]
To             : state.RD_ADDRNEW
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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