getpcmdata.tcl

PCM数据采集

VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 06/18/08 11:46:14 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:46:14 ###########


########## Tcl recorder starts at 06/18/08 11:46:25 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:46:25 ###########


########## Tcl recorder starts at 06/18/08 12:44:13 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 12:44:13 ###########


########## Tcl recorder starts at 06/18/08 12:44:14 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 12:44:14 ###########


########## Tcl recorder starts at 06/18/08 12:45:07 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 12:45:07 ###########


########## Tcl recorder starts at 06/18/08 12:45:16 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 12:45:16 ###########


########## Tcl recorder starts at 06/18/08 13:21:27 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"pcm.vhd\" -o \"pcm.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 13:21:27 ###########


########## Tcl recorder starts at 06/18/08 13:21:28 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=pcm.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open PCM.cmd w} rspFile] {
	puts stderr "Cannot create response file PCM.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: PCM
WORKING_PATH: \"$proj_dir\"
MODULE: PCM
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" pcm.vhd
OUTPUT_FILE_NAME: PCM
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e PCM -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 13:21:28 ###########


########## Tcl recorder starts at 06/18/08 13:23:36 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"pcm.vhd\" -o \"pcm.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 13:23:36 ###########


########## Tcl recorder starts at 06/18/08 13:23:36 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=pcm.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open PCM.cmd w} rspFile] {
	puts stderr "Cannot create response file PCM.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: PCM
WORKING_PATH: \"$proj_dir\"
MODULE: PCM
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" pcm.vhd
OUTPUT_FILE_NAME: PCM
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e PCM -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 13:23:36 ###########


########## Tcl recorder starts at 06/18/08 17:14:24 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 17:14:24 ###########


########## Tcl recorder starts at 06/18/08 17:16:05 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"getpcm.vhd\" -o \"getpcm.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 17:16:05 ###########


########## Tcl recorder starts at 06/18/08 17:16:29 ##########

# Commands to make the Process: 
# Edit Module Generation
# - none -
# Application to view the Process: 
# Edit Module Generation
if [runCmd "\"$cpld_bin/ipexpress\" -dir \"$proj_dir\" -prj getpcmdata -module FIFO_DC.lpc -gui"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 17:16:29 ###########


########## Tcl recorder starts at 06/18/08 17:17:15 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/lpc2jhd\" FIFO_DC.lpc -family LatticeXP2"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 17:17:15 ###########


########## Tcl recorder starts at 06/18/08 17:17:31 ##########

# Commands to make the Process: 
# View Source
# - none -
# Application to view the Process: 
# View Source
if [runCmd "\"$cpld_bin/synview\" -i FIFO_DC.lpc"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 17:17:31 ###########


########## Tcl recorder starts at 06/18/08 17:17:42 ##########

# Commands to make the Process: 
# View Instantiation VHDL Template
if [runCmd "\"$cpld_bin/vhd2naf\" -tfi -proj getpcmdata -mod FIFO_DC -out FIFO_DC -ext vht FIFO_DC.vhd -p \"$install_dir/ispcpld/generic\" -tpl \"$install_dir/ispcpld/generic/vhdl/vhdinst.tft\""] {
	return
} else {
	vwait done