getpcmdata.tcl

来自「PCM数据采集」· TCL 代码 · 共 2,446 行 · 第 1/5 页

TCL
2,446 行
字号
12345
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartRec -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:00:30 ###########


########## Tcl recorder starts at 06/18/08 11:00:57 ##########

# Commands to make the Process: 
# Compile EDIF File
if [runCmd "\"$fpga_bin/edif2ngd\" -l LatticeXP2 -d LFXP2-17E \"UartRec.edi\" \"UartRec.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:00:57 ###########


########## Tcl recorder starts at 06/18/08 11:01:38 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:01:38 ###########


########## Tcl recorder starts at 06/18/08 11:01:41 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:01:41 ###########


########## Tcl recorder starts at 06/18/08 11:03:39 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:03:39 ###########


########## Tcl recorder starts at 06/18/08 11:03:41 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:03:41 ###########


########## Tcl recorder starts at 06/18/08 11:05:34 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:05:34 ###########


########## Tcl recorder starts at 06/18/08 11:05:37 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:05:37 ###########


########## Tcl recorder starts at 06/18/08 11:09:21 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:09:21 ###########


########## Tcl recorder starts at 06/18/08 11:09:30 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:09:30 ###########


########## Tcl recorder starts at 06/18/08 11:18:48 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:18:48 ###########


########## Tcl recorder starts at 06/18/08 11:19:02 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:19:02 ###########


########## Tcl recorder starts at 06/18/08 11:43:16 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:43:16 ###########


########## Tcl recorder starts at 06/18/08 11:43:40 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartsend.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartSend.cmd w} rspFile] {
	puts stderr "Cannot create response file UartSend.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartSend
WORKING_PATH: \"$proj_dir\"
MODULE: UartSend
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartsend.vhd
OUTPUT_FILE_NAME: UartSend
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartSend -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:43:40 ###########


########## Tcl recorder starts at 06/18/08 11:44:22 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartsend.vhd\" -o \"uartsend.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:44:22 ###########


########## Tcl recorder starts at 06/18/08 11:44:25 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
12345

getpcmdata.tcl - 源码说明

本页面展示了「PCM数据采集」中的 getpcmdata.tcl 源码文件，采用 TCL 编程语言编写，共 2,446 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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