getpcmdata.tcl

PCM数据采集

OUTPUT_FILE_NAME: BaudR
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BaudR -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:43:35 ###########


########## Tcl recorder starts at 06/18/08 10:45:32 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"baudr.vhd\" -o \"baudr.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:45:32 ###########


########## Tcl recorder starts at 06/18/08 10:45:33 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=baudr.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open BaudR.cmd w} rspFile] {
	puts stderr "Cannot create response file BaudR.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: BaudR
WORKING_PATH: \"$proj_dir\"
MODULE: BaudR
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" baudr.vhd
OUTPUT_FILE_NAME: BaudR
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BaudR -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:45:33 ###########


########## Tcl recorder starts at 06/18/08 10:46:31 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"baudr.vhd\" -o \"baudr.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:46:31 ###########


########## Tcl recorder starts at 06/18/08 10:46:32 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=baudr.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open BaudR.cmd w} rspFile] {
	puts stderr "Cannot create response file BaudR.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: BaudR
WORKING_PATH: \"$proj_dir\"
MODULE: BaudR
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" baudr.vhd
OUTPUT_FILE_NAME: BaudR
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BaudR -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:46:32 ###########


########## Tcl recorder starts at 06/18/08 10:48:55 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"baudr.vhd\" -o \"baudr.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:48:55 ###########


########## Tcl recorder starts at 06/18/08 10:49:00 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=baudr.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open BaudR.cmd w} rspFile] {
	puts stderr "Cannot create response file BaudR.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: BaudR
WORKING_PATH: \"$proj_dir\"
MODULE: BaudR
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" baudr.vhd
OUTPUT_FILE_NAME: BaudR
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BaudR -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:49:00 ###########


########## Tcl recorder starts at 06/18/08 10:50:54 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=pcm.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open PCM.cmd w} rspFile] {
	puts stderr "Cannot create response file PCM.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: PCM
WORKING_PATH: \"$proj_dir\"
MODULE: PCM
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" pcm.vhd
OUTPUT_FILE_NAME: PCM
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e PCM -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:50:54 ###########


########## Tcl recorder starts at 06/18/08 10:51:43 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"pcm.vhd\" -o \"pcm.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:51:43 ###########


########## Tcl recorder starts at 06/18/08 10:55:41 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"pcm.vhd\" -o \"pcm.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:55:41 ###########


########## Tcl recorder starts at 06/18/08 10:55:45 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=pcm.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open PCM.cmd w} rspFile] {
	puts stderr "Cannot create response file PCM.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: PCM
WORKING_PATH: \"$proj_dir\"
MODULE: PCM
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" pcm.vhd
OUTPUT_FILE_NAME: PCM
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e PCM -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:55:45 ###########


########## Tcl recorder starts at 06/18/08 10:57:10 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartrec.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartRec.cmd w} rspFile] {
	puts stderr "Cannot create response file UartRec.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartRec
WORKING_PATH: \"$proj_dir\"
MODULE: UartRec
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartrec.vhd
OUTPUT_FILE_NAME: UartRec
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:   3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:   0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e UartRec -target LATTICE-XP2 -part LFXP2_17E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 10:57:10 ###########


########## Tcl recorder starts at 06/18/08 11:00:26 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" \"uartrec.vhd\" -o \"uartrec.jhd\" -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/18/08 11:00:26 ###########


########## Tcl recorder starts at 06/18/08 11:00:30 ##########

# Commands to make the Process: 
# Synplify Synthesize VHDL File
if [catch {open getpcmdata.rvp w} rspFile] {
	puts stderr "Cannot create response file getpcmdata.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=getpcmdata.sty
PROJECT=getpcmdata
ENTRY=Pure VHDL
WORKING_PATH=$proj_dir
MODULE=GetPcm
TOP_FILE=getpcm.vhd
EDF_FILE_LIST=uartrec.vhd FIFO_DC.lpc uartsend.vhd baudr.vhd getpcm.vhd pcm.vhd
VHDL_FILE_LIST=uartrec.vhd
VERILOG_FILE_LIST=getpcmdata.h 
DEVICEPART=LFXP2-17E-5Q208CES
"
	close $rspFile
}
if [catch {open UartRec.cmd w} rspFile] {
	puts stderr "Cannot create response file UartRec.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: getpcmdata.sty
PROJECT: UartRec
WORKING_PATH: \"$proj_dir\"
MODULE: UartRec
VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd\" uartrec.vhd
OUTPUT_FILE_NAME: UartRec
SUFFIX_NAME: edi
WRITE_PRF: false
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true