prev_cmp_clock.tan.qmsg

基于VHDL的电子钟 实现一个简单的电子钟

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt60:sec\|carry " "Info: Detected ripple clock \"cnt60:sec\|carry\" as buffer" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 8 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt60:sec\|carry" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt60:min\|carry " "Info: Detected ripple clock \"cnt60:min\|carry\" as buffer" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 8 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt60:min\|carry" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk2 register register decode\[0\]~reg0 tempt\[3\] 275.03 MHz Internal " "Info: Clock \"clk2\" Internal fmax is restricted to 275.03 MHz between source register \"decode\[0\]~reg0\" and destination register \"tempt\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.168 ns + Longest register register " "Info: + Longest register to register delay is 3.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decode\[0\]~reg0 1 REG LC_X16_Y8_N7 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y8_N7; Fanout = 12; REG Node = 'decode\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { decode[0]~reg0 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.292 ns) 1.677 ns Mux0~237 2 COMB LC_X12_Y8_N6 1 " "Info: 2: + IC(1.385 ns) + CELL(0.292 ns) = 1.677 ns; Loc. = LC_X12_Y8_N6; Fanout = 1; COMB Node = 'Mux0~237'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.677 ns" { decode[0]~reg0 Mux0~237 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.973 ns Mux0~238 3 COMB LC_X12_Y8_N7 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.973 ns; Loc. = LC_X12_Y8_N7; Fanout = 1; COMB Node = 'Mux0~238'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux0~237 Mux0~238 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.738 ns) 3.168 ns tempt\[3\] 4 REG LC_X12_Y8_N3 7 " "Info: 4: + IC(0.457 ns) + CELL(0.738 ns) = 3.168 ns; Loc. = LC_X12_Y8_N3; Fanout = 7; REG Node = 'tempt\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.195 ns" { Mux0~238 tempt[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.144 ns ( 36.11 % ) " "Info: Total cell delay = 1.144 ns ( 36.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.024 ns ( 63.89 % ) " "Info: Total interconnect delay = 2.024 ns ( 63.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { decode[0]~reg0 Mux0~237 Mux0~238 tempt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.168 ns" { decode[0]~reg0 {} Mux0~237 {} Mux0~238 {} tempt[3] {} } { 0.000ns 1.385ns 0.182ns 0.457ns } { 0.000ns 0.292ns 0.114ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.042 ns - Smallest " "Info: - Smallest clock skew is -0.042 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock \"clk2\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk2 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns tempt\[3\] 2 REG LC_X12_Y8_N3 7 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y8_N3; Fanout = 7; REG Node = 'tempt\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk2 tempt[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 tempt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk2 {} clk2~out0 {} tempt[3] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk2\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk2 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns decode\[0\]~reg0 2 REG LC_X16_Y8_N7 12 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y8_N7; Fanout = 12; REG Node = 'decode\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk2 decode[0]~reg0 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk2 decode[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk2 {} clk2~out0 {} decode[0]~reg0 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 tempt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk2 {} clk2~out0 {} tempt[3] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk2 decode[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk2 {} clk2~out0 {} decode[0]~reg0 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { decode[0]~reg0 Mux0~237 Mux0~238 tempt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.168 ns" { decode[0]~reg0 {} Mux0~237 {} Mux0~238 {} tempt[3] {} } { 0.000ns 1.385ns 0.182ns 0.457ns } { 0.000ns 0.292ns 0.114ns 0.738ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 tempt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk2 {} clk2~out0 {} tempt[3] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk2 decode[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk2 {} clk2~out0 {} decode[0]~reg0 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { tempt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { tempt[3] {} } {  } {  } "" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt60:sec\|cl\[0\] cnt60:sec\|ch\[0\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"cnt60:sec\|cl\[0\]\" and destination register \"cnt60:sec\|ch\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.226 ns + Longest register register " "Info: + Longest register to register delay is 3.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt60:sec\|cl\[0\] 1 REG LC_X12_Y8_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N2; Fanout = 6; REG Node = 'cnt60:sec\|cl\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt60:sec|cl[0] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.590 ns) 1.177 ns cnt60:sec\|Equal0~37 2 COMB LC_X12_Y8_N0 5 " "Info: 2: + IC(0.587 ns) + CELL(0.590 ns) = 1.177 ns; Loc. = LC_X12_Y8_N0; Fanout = 5; COMB Node = 'cnt60:sec\|Equal0~37'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.177 ns" { cnt60:sec|cl[0] cnt60:sec|Equal0~37 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.867 ns) 3.226 ns cnt60:sec\|ch\[0\] 3 REG LC_X8_Y8_N4 6 " "Info: 3: + IC(1.182 ns) + CELL(0.867 ns) = 3.226 ns; Loc. = LC_X8_Y8_N4; Fanout = 6; REG Node = 'cnt60:sec\|ch\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { cnt60:sec|Equal0~37 cnt60:sec|ch[0] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 45.16 % ) " "Info: Total cell delay = 1.457 ns ( 45.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.769 ns ( 54.84 % ) " "Info: Total interconnect delay = 1.769 ns ( 54.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.226 ns" { cnt60:sec|cl[0] cnt60:sec|Equal0~37 cnt60:sec|ch[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.226 ns" { cnt60:sec|cl[0] {} cnt60:sec|Equal0~37 {} cnt60:sec|ch[0] {} } { 0.000ns 0.587ns 1.182ns } { 0.000ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns cnt60:sec\|ch\[0\] 2 REG LC_X8_Y8_N4 6 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X8_Y8_N4; Fanout = 6; REG Node = 'cnt60:sec\|ch\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk cnt60:sec|ch[0] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk cnt60:sec|ch[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk {} clk~out0 {} cnt60:sec|ch[0] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns cnt60:sec\|cl\[0\] 2 REG LC_X12_Y8_N2 6 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y8_N2; Fanout = 6; REG Node = 'cnt60:sec\|cl\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk cnt60:sec|cl[0] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk cnt60:sec|cl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk {} clk~out0 {} cnt60:sec|cl[0] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk cnt60:sec|ch[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk {} clk~out0 {} cnt60:sec|ch[0] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk cnt60:sec|cl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk {} clk~out0 {} cnt60:sec|cl[0] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.226 ns" { cnt60:sec|cl[0] cnt60:sec|Equal0~37 cnt60:sec|ch[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.226 ns" { cnt60:sec|cl[0] {} cnt60:sec|Equal0~37 {} cnt60:sec|ch[0] {} } { 0.000ns 0.587ns 1.182ns } { 0.000ns 0.590ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk cnt60:sec|ch[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk {} clk~out0 {} cnt60:sec|ch[0] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk cnt60:sec|cl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk {} clk~out0 {} cnt60:sec|cl[0] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt60:sec|ch[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { cnt60:sec|ch[0] {} } {  } {  } "" } } { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk2 decode\[2\] decode\[2\]~reg0 7.864 ns register " "Info: tco from clock \"clk2\" to destination pin \"decode\[2\]\" through register \"decode\[2\]~reg0\" is 7.864 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 2.740 ns + Longest register " "Info: + Longest clock path from clock \"clk2\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk2 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns decode\[2\]~reg0 2 REG LC_X12_Y8_N8 6 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y8_N8; Fanout = 6; REG Node = 'decode\[2\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk2 decode[2]~reg0 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 decode[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk2 {} clk2~out0 {} decode[2]~reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns + Longest register pin " "Info: + Longest register to pin delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decode\[2\]~reg0 1 REG LC_X12_Y8_N8 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N8; Fanout = 6; REG Node = 'decode\[2\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { decode[2]~reg0 } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.792 ns) + CELL(2.108 ns) 4.900 ns decode\[2\] 2 PIN PIN_55 0 " "Info: 2: + IC(2.792 ns) + CELL(2.108 ns) = 4.900 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'decode\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { decode[2]~reg0 decode[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 43.02 % ) " "Info: Total cell delay = 2.108 ns ( 43.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.792 ns ( 56.98 % ) " "Info: Total interconnect delay = 2.792 ns ( 56.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { decode[2]~reg0 decode[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { decode[2]~reg0 {} decode[2] {} } { 0.000ns 2.792ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 decode[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk2 {} clk2~out0 {} decode[2]~reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { decode[2]~reg0 decode[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { decode[2]~reg0 {} decode[2] {} } { 0.000ns 2.792ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}