idct.map.qmsg

8x8 iDCT verilog code 一次輸入八個點

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(110) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(110): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(111) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(111): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B4DM_n17 matix_mul_8x8_n17:matix_mul_8x8_n17\|B4DM_n17:B4DM0 " "Info: Elaborating entity \"B4DM_n17\" for hierarchy \"matix_mul_8x8_n17:matix_mul_8x8_n17\|B4DM_n17:B4DM0\"" {  } { { "matix_mul_8x8_n17.v" "B4DM0" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 B4DM_n17.v(14) " "Warning (10230): Verilog HDL assignment warning at B4DM_n17.v(14): truncated value with size 32 to match size of target (17)" {  } { { "B4DM_n17.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n17.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 B4DM_n17.v(15) " "Warning (10230): Verilog HDL assignment warning at B4DM_n17.v(15): truncated value with size 32 to match size of target (17)" {  } { { "B4DM_n17.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n17.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 B4DM_n17.v(16) " "Warning (10230): Verilog HDL assignment warning at B4DM_n17.v(16): truncated value with size 32 to match size of target (17)" {  } { { "B4DM_n17.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n17.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 B4DM_n17.v(17) " "Warning (10230): Verilog HDL assignment warning at B4DM_n17.v(17): truncated value with size 32 to match size of target (17)" {  } { { "B4DM_n17.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n17.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "matix_mul_8x8_n19 matix_mul_8x8_n19:matix_mul_8x8_n19 " "Info: Elaborating entity \"matix_mul_8x8_n19\" for hierarchy \"matix_mul_8x8_n19:matix_mul_8x8_n19\"" {  } { { "IDCT.v" "matix_mul_8x8_n19" { Text "D:/verilog/idct/IDCT/IDCT.v" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(104) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(104): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(105) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(105): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(106) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(106): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(107) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(107): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(108) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(108): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(109) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(109): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(110) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(110): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 21 matix_mul_8x8_n19.v(111) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n19.v(111): truncated value with size 23 to match size of target (21)" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B4DM_n19 matix_mul_8x8_n19:matix_mul_8x8_n19\|B4DM_n19:B4DM0 " "Info: Elaborating entity \"B4DM_n19\" for hierarchy \"matix_mul_8x8_n19:matix_mul_8x8_n19\|B4DM_n19:B4DM0\"" {  } { { "matix_mul_8x8_n19.v" "B4DM0" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 B4DM_n19.v(14) " "Warning (10230): Verilog HDL assignment warning at B4DM_n19.v(14): truncated value with size 32 to match size of target (19)" {  } { { "B4DM_n19.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n19.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 B4DM_n19.v(15) " "Warning (10230): Verilog HDL assignment warning at B4DM_n19.v(15): truncated value with size 32 to match size of target (19)" {  } { { "B4DM_n19.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n19.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 B4DM_n19.v(16) " "Warning (10230): Verilog HDL assignment warning at B4DM_n19.v(16): truncated value with size 32 to match size of target (19)" {  } { { "B4DM_n19.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n19.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 B4DM_n19.v(17) " "Warning (10230): Verilog HDL assignment warning at B4DM_n19.v(17): truncated value with size 32 to match size of target (19)" {  } { { "B4DM_n19.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n19.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d0\[0\] " "Warning: No output dependent on input pin \"d0\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d1\[0\] " "Warning: No output dependent on input pin \"d1\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d2\[0\] " "Warning: No output dependent on input pin \"d2\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d3\[0\] " "Warning: No output dependent on input pin \"d3\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d4\[0\] " "Warning: No output dependent on input pin \"d4\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d5\[0\] " "Warning: No output dependent on input pin \"d5\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d6\[0\] " "Warning: No output dependent on input pin \"d6\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d7\[0\] " "Warning: No output dependent on input pin \"d7\[0\]\"" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4748 " "Info: Implemented 4748 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "138 " "Info: Implemented 138 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "329 " "Info: Implemented 329 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "4281 " "Info: Implemented 4281 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 41 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Info: Allocated 151 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 15 20:07:48 2008 " "Info: Processing ended: Sun Jun 15 20:07:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}