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📄 prev_cmp_idct.qmsg

📁 8x8 iDCT verilog code 一次輸入八個點
💻 QMSG
📖 第 1 页 / 共 5 页
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(43) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(43): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(44) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(44): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(45) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(45): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(46) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(46): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(47) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(47): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "F " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"F\" into its bus" {  } {  } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "matix_mul_8x8_n17 matix_mul_8x8_n17:matix_mul_8x8_n17 " "Info: Elaborating entity \"matix_mul_8x8_n17\" for hierarchy \"matix_mul_8x8_n17:matix_mul_8x8_n17\"" {  } { { "IDCT.v" "matix_mul_8x8_n17" { Text "D:/verilog/idct/IDCT/IDCT.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(104) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(104): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(105) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(105): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(106) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(106): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(107) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(107): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 19 matix_mul_8x8_n17.v(108) " "Warning (10230): Verilog HDL assignment warning at matix_mul_8x8_n17.v(108): truncated value with size 21 to match size of target (19)" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}

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