prev_cmp_idct.qmsg

8x8 iDCT verilog code 一次輸入八個點

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 15 20:07:24 2008 " "Info: Processing started: Sun Jun 15 20:07:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off IDCT -c IDCT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off IDCT -c IDCT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "B4DM_n17.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file B4DM_n17.v" { { "Info" "ISGN_ENTITY_NAME" "1 B4DM_n17 " "Info: Found entity 1: B4DM_n17" {  } { { "B4DM_n17.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n17.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "B4DM_n19.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file B4DM_n19.v" { { "Info" "ISGN_ENTITY_NAME" "1 B4DM_n19 " "Info: Found entity 1: B4DM_n19" {  } { { "B4DM_n19.v" "" { Text "D:/verilog/idct/IDCT/B4DM_n19.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "IDCT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file IDCT.v" { { "Info" "ISGN_ENTITY_NAME" "1 IDCT " "Info: Found entity 1: IDCT" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "matix_mul_8x8_n17.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file matix_mul_8x8_n17.v" { { "Info" "ISGN_ENTITY_NAME" "1 matix_mul_8x8_n17 " "Info: Found entity 1: matix_mul_8x8_n17" {  } { { "matix_mul_8x8_n17.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n17.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "matix_mul_8x8_n19.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file matix_mul_8x8_n19.v" { { "Info" "ISGN_ENTITY_NAME" "1 matix_mul_8x8_n19 " "Info: Found entity 1: matix_mul_8x8_n19" {  } { { "matix_mul_8x8_n19.v" "" { Text "D:/verilog/idct/IDCT/matix_mul_8x8_n19.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "IDCT " "Info: Elaborating entity \"IDCT\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(40) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(40): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(41) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(41): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 IDCT.v(42) " "Warning (10230): Verilog HDL assignment warning at IDCT.v(42): truncated value with size 32 to match size of target (19)" {  } { { "IDCT.v" "" { Text "D:/verilog/idct/IDCT/IDCT.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}