sram_2.hif

8x8DCT verilog code 一次輸入8個點

DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
c:|altera|71|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
CLK_10MHZ:M1|altpll:altpll_component
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|SRAM_2.(3).cnf
db|SRAM_2.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|sld_signaltap.vhd
a281ce8811fa577621745480c746be3d
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
671116800
PARAMETER_UNKNOWN
USR
sld_ip_version
5
PARAMETER_SIGNED_DEC
DEF
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
DEF
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
68
PARAMETER_UNKNOWN
USR
sld_trigger_bits
68
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
7
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
22255
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
18136
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
1024
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
10
PARAMETER_UNKNOWN
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
223
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|SRAM_2.(4).cnf
db|SRAM_2.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|sld_signaltap.vhd
a281ce8811fa577621745480c746be3d
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
5
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
68
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
68
PARAMETER_SIGNED_DEC
USR
sld_data_bit_cntr_bits
7
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
22255
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
18136
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
1024
PARAMETER_SIGNED_DEC
USR
sld_mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
223
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(acq_data_in)
67 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
67 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
67 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
67 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|SRAM_2.(5).cnf
db|SRAM_2.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|sld_ela_control.vhd
c344b9ef4eed6f1fb9dd17ea42ba423
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
68
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
enable_clk_edge_def
0
PARAMETER_SIGNED_DEC
USR
enable_async_glitch
0
PARAMETER_SIGNED_DEC
USR
enable_sync_normal
1
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
sample_depth
1024
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
223
PARAMETER_SIGNED_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(acq_trigger_in)
67 downto 0
PARAMETER_STRING
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|SRAM_2.(6).cnf
db|SRAM_2.(6).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|lpm_shiftreg.tdf
3afc744803f77b6fa5676c390d0fb8f
6
# user_parameter {
LPM_WIDTH
19
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
load
-1
1
data9
-1
1
data8
-1
1
data7
-1
1
data6
-1
1
data5
-1
1
data4
-1
1
data3
-1
1
data2
-1
1
data18
-1
1
data17
-1
1
data16
-1
1
data15
-1
1
data14
-1
1
data13
-1
1
data12
-1
1
data11
-1
1
data10
-1
1
data1
-1
1
data0
-1
1
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
c:|altera|71|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|SRAM_2.(7).cnf
db|SRAM_2.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|sld_ela_control.vhd
c344b9ef4eed6f1fb9dd17ea42ba423
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
68
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
223
PARAMETER_SIGNED_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
67 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_ena)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|SRAM_2.(8).cnf
db|SRAM_2.(8).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|lpm_shiftreg.tdf
3afc744803f77b6fa5676c390d0fb8f
6
# user_parameter {
LPM_WIDTH
204
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q99
-1
3
q98
-1
3
q97
-1
3
q96
-1
3
q95
-1
3
q94
-1
3
q93
-1
3
q92
-1
3
q91
-1
3
q90
-1
3
q9
-1
3
q89
-1
3
q88
-1
3
q87
-1
3
q86
-1
3
q85
-1
3
q84
-1
3
q83
-1
3
q82
-1
3
q81
-1
3
q80
-1
3
q8
-1
3
q79
-1
3
q78
-1
3
q77
-1
3
q76
-1
3
q75
-1
3
q74
-1
3
q73
-1
3
q72
-1
3
q71
-1
3
q70
-1
3
q7
-1
3
q69
-1
3
q68
-1
3
q67
-1
3
q66
-1
3
q65
-1
3
q64
-1
3
q63
-1
3
q62
-1
3
q61
-1
3
q60
-1
3
q6
-1
3
q59
-1
3
q58
-1
3
q57
-1
3
q56
-1
3
q55
-1
3
q54
-1
3
q53
-1
3
q52
-1
3
q51
-1
3
q50
-1
3
q5
-1
3
q49
-1
3
q48
-1
3
q47
-1
3
q46
-1
3
q45
-1
3
q44
-1
3
q43
-1
3
q42
-1
3
q41
-1
3
q40
-1
3
q4
-1
3
q39
-1
3
q38
-1
3
q37
-1
3
q36
-1
3
q35
-1
3
q34
-1
3
q33
-1
3
q32
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q203
-1
3
q202
-1
3
q201
-1
3
q200
-1
3
q20
-1
3
q2
-1
3
q199
-1
3
q198
-1
3
q197
-1
3
q196
-1
3
q195
-1
3
q194
-1
3
q193
-1
3
q192
-1
3
q191
-1
3
q190
-1
3
q19
-1
3
q189
-1
3
q188
-1
3
q187
-1
3
q186
-1
3
q185
-1
3
q184
-1
3
q183
-1
3
q182
-1
3
q181
-1
3
q180
-1
3
q18
-1
3
q179
-1
3
q178
-1
3
q177
-1
3
q176
-1
3
q175
-1
3
q174
-1
3
q173
-1
3
q172
-1
3
q171
-1
3