sram_2.hier_info

8x8DCT verilog code 一次輸入8個點

|SRAM_2
HEX0[0] <= HEX0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[1] <= HEX0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[2] <= HEX0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[3] <= HEX0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[4] <= HEX0[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[5] <= HEX0[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[6] <= HEX0[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[0] <= HEX1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[1] <= HEX1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[2] <= HEX1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[3] <= HEX1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[4] <= HEX1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[5] <= HEX1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[6] <= HEX1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[0] <= HEX2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[1] <= HEX2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[2] <= HEX2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[3] <= HEX2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[4] <= HEX2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[5] <= HEX2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX2[6] <= HEX2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[0] <= HEX3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[1] <= HEX3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[2] <= HEX3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[3] <= HEX3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[4] <= HEX3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[5] <= HEX3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HEX3[6] <= HEX3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LEDG[0] <= LEDG[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= <GND>
LEDG[2] <= <GND>
LEDG[3] <= <GND>
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
LEDG[8] <= <GND>
LEDR[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
LEDR[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE
LEDR[4] <= SW[4].DB_MAX_OUTPUT_PORT_TYPE
LEDR[5] <= SW[5].DB_MAX_OUTPUT_PORT_TYPE
LEDR[6] <= SW[6].DB_MAX_OUTPUT_PORT_TYPE
LEDR[7] <= SW[7].DB_MAX_OUTPUT_PORT_TYPE
LEDR[8] <= SW[8].DB_MAX_OUTPUT_PORT_TYPE
LEDR[9] <= SW[9].DB_MAX_OUTPUT_PORT_TYPE
LEDR[10] <= SW[10].DB_MAX_OUTPUT_PORT_TYPE
LEDR[11] <= SW[11].DB_MAX_OUTPUT_PORT_TYPE
LEDR[12] <= SW[12].DB_MAX_OUTPUT_PORT_TYPE
LEDR[13] <= SW[13].DB_MAX_OUTPUT_PORT_TYPE
LEDR[14] <= SW[14].DB_MAX_OUTPUT_PORT_TYPE
LEDR[15] <= SW[15].DB_MAX_OUTPUT_PORT_TYPE
LEDR[16] <= SW[16].DB_MAX_OUTPUT_PORT_TYPE
LEDR[17] <= SW[17].DB_MAX_OUTPUT_PORT_TYPE
SW[0] => LEDR[0].DATAIN
SW[1] => LEDR[1].DATAIN
SW[2] => LEDR[2].DATAIN
SW[3] => LEDR[3].DATAIN
SW[4] => LEDR[4].DATAIN
SW[5] => LEDR[5].DATAIN
SW[6] => LEDR[6].DATAIN
SW[7] => LEDR[7].DATAIN
SW[8] => LEDR[8].DATAIN
SW[9] => LEDR[9].DATAIN
SW[10] => LEDR[10].DATAIN
SW[11] => LEDR[11].DATAIN
SW[12] => LEDR[12].DATAIN
SW[13] => LEDR[13].DATAIN
SW[14] => LEDR[14].DATAIN
SW[15] => LEDR[15].DATAIN
SW[16] => LEDR[16].DATAIN
SW[17] => LEDR[17].DATAIN
KEY[0] => always0~0.IN0
KEY[0] => SRAM_WE_N.DATAIN
KEY[1] => ~NO_FANOUT~
KEY[2] => SRAM_DQ[15]~16.IN0
KEY[2] => tmp_addr~53.OUTPUTSELECT
KEY[2] => tmp_addr~52.OUTPUTSELECT
KEY[2] => tmp_addr~51.OUTPUTSELECT
KEY[2] => tmp_addr~50.OUTPUTSELECT
KEY[2] => tmp_addr~49.OUTPUTSELECT
KEY[2] => tmp_addr~48.OUTPUTSELECT
KEY[2] => tmp_addr~47.OUTPUTSELECT
KEY[2] => tmp_addr~46.OUTPUTSELECT
KEY[2] => tmp_addr~45.OUTPUTSELECT
KEY[2] => tmp_addr~44.OUTPUTSELECT
KEY[2] => tmp_addr~43.OUTPUTSELECT
KEY[2] => tmp_addr~42.OUTPUTSELECT
KEY[2] => tmp_addr~41.OUTPUTSELECT
KEY[2] => tmp_addr~40.OUTPUTSELECT
KEY[2] => tmp_addr~39.OUTPUTSELECT
KEY[2] => tmp_addr~38.OUTPUTSELECT
KEY[2] => tmp_addr~37.OUTPUTSELECT
KEY[2] => tmp_addr~36.OUTPUTSELECT
KEY[2] => SRAM_ADDR~53.OUTPUTSELECT
KEY[2] => SRAM_ADDR~52.OUTPUTSELECT
KEY[2] => SRAM_ADDR~51.OUTPUTSELECT
KEY[2] => SRAM_ADDR~50.OUTPUTSELECT
KEY[2] => SRAM_ADDR~49.OUTPUTSELECT
KEY[2] => SRAM_ADDR~48.OUTPUTSELECT
KEY[2] => SRAM_ADDR~47.OUTPUTSELECT
KEY[2] => SRAM_ADDR~46.OUTPUTSELECT
KEY[2] => SRAM_ADDR~45.OUTPUTSELECT
KEY[2] => SRAM_ADDR~44.OUTPUTSELECT
KEY[2] => SRAM_ADDR~43.OUTPUTSELECT
KEY[2] => SRAM_ADDR~42.OUTPUTSELECT
KEY[2] => SRAM_ADDR~41.OUTPUTSELECT
KEY[2] => SRAM_ADDR~40.OUTPUTSELECT
KEY[2] => SRAM_ADDR~39.OUTPUTSELECT
KEY[2] => SRAM_ADDR~38.OUTPUTSELECT
KEY[2] => SRAM_ADDR~37.OUTPUTSELECT
KEY[2] => SRAM_ADDR~36.OUTPUTSELECT
KEY[2] => SRAM_OE_N.DATAIN
KEY[2] => HEX2[0]~reg0.ENA
KEY[2] => HEX3[6]~reg0.ENA
KEY[2] => HEX3[5]~reg0.ENA
KEY[2] => HEX3[4]~reg0.ENA
KEY[2] => HEX3[3]~reg0.ENA
KEY[2] => HEX3[2]~reg0.ENA
KEY[2] => HEX3[1]~reg0.ENA
KEY[2] => HEX3[0]~reg0.ENA
KEY[2] => HEX2[1]~reg0.ENA
KEY[2] => HEX2[2]~reg0.ENA
KEY[2] => HEX2[3]~reg0.ENA
KEY[2] => HEX2[4]~reg0.ENA
KEY[2] => HEX2[5]~reg0.ENA
KEY[2] => HEX2[6]~reg0.ENA
KEY[2] => HEX1[0]~reg0.ENA
KEY[2] => HEX1[1]~reg0.ENA
KEY[2] => HEX1[2]~reg0.ENA
KEY[2] => HEX1[3]~reg0.ENA
KEY[2] => HEX1[4]~reg0.ENA
KEY[2] => HEX1[5]~reg0.ENA
KEY[2] => HEX1[6]~reg0.ENA
KEY[2] => HEX0[0]~reg0.ENA
KEY[2] => HEX0[1]~reg0.ENA
KEY[2] => HEX0[2]~reg0.ENA
KEY[2] => HEX0[3]~reg0.ENA
KEY[2] => HEX0[4]~reg0.ENA
KEY[2] => HEX0[5]~reg0.ENA
KEY[2] => HEX0[6]~reg0.ENA
KEY[2] => data_out[0]~reg0.ENA
KEY[2] => data_out[1]~reg0.ENA
KEY[2] => data_out[2]~reg0.ENA
KEY[2] => data_out[3]~reg0.ENA
KEY[2] => data_out[4]~reg0.ENA
KEY[2] => data_out[5]~reg0.ENA
KEY[2] => data_out[6]~reg0.ENA
KEY[2] => data_out[7]~reg0.ENA
KEY[2] => data_out[8]~reg0.ENA
KEY[2] => data_out[9]~reg0.ENA
KEY[2] => data_out[10]~reg0.ENA
KEY[2] => data_out[11]~reg0.ENA
KEY[2] => data_out[12]~reg0.ENA
KEY[2] => data_out[13]~reg0.ENA
KEY[2] => data_out[14]~reg0.ENA
KEY[2] => data_out[15]~reg0.ENA
KEY[2] => SRAM_DQ[0]~en.DATAIN
KEY[2] => SRAM_DQ[1]~en.DATAIN
KEY[2] => SRAM_DQ[2]~en.DATAIN
KEY[2] => SRAM_DQ[3]~en.DATAIN
KEY[2] => SRAM_DQ[4]~en.DATAIN
KEY[2] => SRAM_DQ[5]~en.DATAIN
KEY[2] => SRAM_DQ[6]~en.DATAIN
KEY[2] => SRAM_DQ[7]~en.DATAIN
KEY[2] => SRAM_DQ[8]~en.DATAIN
KEY[2] => SRAM_DQ[9]~en.DATAIN
KEY[2] => SRAM_DQ[10]~en.DATAIN
KEY[2] => SRAM_DQ[11]~en.DATAIN
KEY[2] => SRAM_DQ[12]~en.DATAIN
KEY[2] => SRAM_DQ[13]~en.DATAIN
KEY[2] => SRAM_DQ[14]~en.DATAIN
KEY[2] => SRAM_DQ[15]~en.DATAIN
KEY[3] => LEDG~0.OUTPUTSELECT
KEY[3] => SRAM_DQ[15]~15.IN0
KEY[3] => SRAM_ADDR~35.OUTPUTSELECT
KEY[3] => SRAM_ADDR~34.OUTPUTSELECT
KEY[3] => SRAM_ADDR~33.OUTPUTSELECT
KEY[3] => SRAM_ADDR~32.OUTPUTSELECT
KEY[3] => SRAM_ADDR~31.OUTPUTSELECT
KEY[3] => SRAM_ADDR~30.OUTPUTSELECT
KEY[3] => SRAM_ADDR~29.OUTPUTSELECT
KEY[3] => SRAM_ADDR~28.OUTPUTSELECT
KEY[3] => SRAM_ADDR~27.OUTPUTSELECT
KEY[3] => SRAM_ADDR~26.OUTPUTSELECT
KEY[3] => SRAM_ADDR~25.OUTPUTSELECT
KEY[3] => SRAM_ADDR~24.OUTPUTSELECT
KEY[3] => SRAM_ADDR~23.OUTPUTSELECT
KEY[3] => SRAM_ADDR~22.OUTPUTSELECT
KEY[3] => SRAM_ADDR~21.OUTPUTSELECT
KEY[3] => SRAM_ADDR~20.OUTPUTSELECT
KEY[3] => SRAM_ADDR~19.OUTPUTSELECT
KEY[3] => SRAM_ADDR~18.OUTPUTSELECT
KEY[3] => tmp_data~31.OUTPUTSELECT
KEY[3] => tmp_data~30.OUTPUTSELECT
KEY[3] => tmp_data~29.OUTPUTSELECT
KEY[3] => tmp_data~28.OUTPUTSELECT
KEY[3] => tmp_data~27.OUTPUTSELECT
KEY[3] => tmp_data~26.OUTPUTSELECT
KEY[3] => tmp_data~25.OUTPUTSELECT
KEY[3] => tmp_data~24.OUTPUTSELECT
KEY[3] => tmp_data~23.OUTPUTSELECT
KEY[3] => tmp_data~22.OUTPUTSELECT
KEY[3] => tmp_data~21.OUTPUTSELECT
KEY[3] => tmp_data~20.OUTPUTSELECT
KEY[3] => tmp_data~19.OUTPUTSELECT
KEY[3] => tmp_data~18.OUTPUTSELECT
KEY[3] => tmp_data~17.OUTPUTSELECT
KEY[3] => tmp_data~16.OUTPUTSELECT
KEY[3] => tmp_addr~35.OUTPUTSELECT
KEY[3] => tmp_addr~34.OUTPUTSELECT
KEY[3] => tmp_addr~33.OUTPUTSELECT
KEY[3] => tmp_addr~32.OUTPUTSELECT
KEY[3] => tmp_addr~31.OUTPUTSELECT
KEY[3] => tmp_addr~30.OUTPUTSELECT
KEY[3] => tmp_addr~29.OUTPUTSELECT
KEY[3] => tmp_addr~28.OUTPUTSELECT
KEY[3] => tmp_addr~27.OUTPUTSELECT
KEY[3] => tmp_addr~26.OUTPUTSELECT
KEY[3] => tmp_addr~25.OUTPUTSELECT
KEY[3] => tmp_addr~24.OUTPUTSELECT
KEY[3] => tmp_addr~23.OUTPUTSELECT
KEY[3] => tmp_addr~22.OUTPUTSELECT
KEY[3] => tmp_addr~21.OUTPUTSELECT
KEY[3] => tmp_addr~20.OUTPUTSELECT
KEY[3] => tmp_addr~19.OUTPUTSELECT
KEY[3] => tmp_addr~18.OUTPUTSELECT
CLOCK_50 => CLOCK_50~0.IN1
SRAM_DQ[0] <= SRAM_DQ[0]~0
SRAM_DQ[1] <= SRAM_DQ[1]~1
SRAM_DQ[2] <= SRAM_DQ[2]~2
SRAM_DQ[3] <= SRAM_DQ[3]~3
SRAM_DQ[4] <= SRAM_DQ[4]~4
SRAM_DQ[5] <= SRAM_DQ[5]~5
SRAM_DQ[6] <= SRAM_DQ[6]~6
SRAM_DQ[7] <= SRAM_DQ[7]~7
SRAM_DQ[8] <= SRAM_DQ[8]~8
SRAM_DQ[9] <= SRAM_DQ[9]~9
SRAM_DQ[10] <= SRAM_DQ[10]~10
SRAM_DQ[11] <= SRAM_DQ[11]~11
SRAM_DQ[12] <= SRAM_DQ[12]~12
SRAM_DQ[13] <= SRAM_DQ[13]~13
SRAM_DQ[14] <= SRAM_DQ[14]~14
SRAM_DQ[15] <= SRAM_DQ[15]~17
SRAM_ADDR[0] <= SRAM_ADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[1] <= SRAM_ADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[2] <= SRAM_ADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[3] <= SRAM_ADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[4] <= SRAM_ADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[5] <= SRAM_ADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[6] <= SRAM_ADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[7] <= SRAM_ADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[8] <= SRAM_ADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[9] <= SRAM_ADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[10] <= SRAM_ADDR[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[11] <= SRAM_ADDR[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[12] <= SRAM_ADDR[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[13] <= SRAM_ADDR[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[14] <= SRAM_ADDR[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[15] <= SRAM_ADDR[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[16] <= SRAM_ADDR[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[17] <= SRAM_ADDR[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_CE_N <= <GND>
SRAM_OE_N <= KEY[2].DB_MAX_OUTPUT_PORT_TYPE
SRAM_WE_N <= KEY[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SRAM_2|CLK_10MHZ:M1
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|SRAM_2|CLK_10MHZ:M1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~2.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>