prev_cmp_sram_2.tan.qmsg

8x8DCT verilog code 一次輸入8個點

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 123.82 MHz 8.076 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 123.82 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 8.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.821 ns + Longest register register " "Info: + Longest register to register delay is 3.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 1 REG LCFF_X22_Y17_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y17_N7; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.420 ns) 1.449 ns sld_hub:sld_hub_inst\|hub_tdo_reg~758 2 COMB LCCOMB_X19_Y13_N12 1 " "Info: 2: + IC(1.029 ns) + CELL(0.420 ns) = 1.449 ns; Loc. = LCCOMB_X19_Y13_N12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~758'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.449 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~758 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.438 ns) 2.643 ns sld_hub:sld_hub_inst\|hub_tdo_reg~760 3 COMB LCCOMB_X20_Y17_N12 1 " "Info: 3: + IC(0.756 ns) + CELL(0.438 ns) = 2.643 ns; Loc. = LCCOMB_X20_Y17_N12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~760'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.194 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~758 sld_hub:sld_hub_inst|hub_tdo_reg~760 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.438 ns) 3.344 ns sld_hub:sld_hub_inst\|hub_tdo_reg~762 4 COMB LCCOMB_X20_Y17_N10 1 " "Info: 4: + IC(0.263 ns) + CELL(0.438 ns) = 3.344 ns; Loc. = LCCOMB_X20_Y17_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~762'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.701 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.150 ns) 3.737 ns sld_hub:sld_hub_inst\|hub_tdo_reg~763 5 COMB LCCOMB_X20_Y17_N14 1 " "Info: 5: + IC(0.243 ns) + CELL(0.150 ns) = 3.737 ns; Loc. = LCCOMB_X20_Y17_N14; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~763'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.821 ns sld_hub:sld_hub_inst\|hub_tdo_reg 6 REG LCFF_X20_Y17_N15 2 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.821 ns; Loc. = LCFF_X20_Y17_N15; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.530 ns ( 40.04 % ) " "Info: Total cell delay = 1.530 ns ( 40.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.291 ns ( 59.96 % ) " "Info: Total interconnect delay = 2.291 ns ( 59.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.821 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~758 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.821 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~758 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 1.029ns 0.756ns 0.263ns 0.243ns 0.000ns } { 0.000ns 0.420ns 0.438ns 0.438ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.003 ns - Smallest " "Info: - Smallest clock skew is -0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.459 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 685 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G1; Fanout = 685; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 4.459 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X20_Y17_N15 2 " "Info: 3: + IC(1.034 ns) + CELL(0.537 ns) = 4.459 ns; Loc. = LCFF_X20_Y17_N15; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.04 % ) " "Info: Total cell delay = 0.537 ns ( 12.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.922 ns ( 87.96 % ) " "Info: Total interconnect delay = 3.922 ns ( 87.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.459 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.459 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 2.888ns 1.034ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.462 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 685 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G1; Fanout = 685; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 4.462 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 3 REG LCFF_X22_Y17_N7 1 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 4.462 ns; Loc. = LCFF_X22_Y17_N7; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.03 % ) " "Info: Total cell delay = 0.537 ns ( 12.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.925 ns ( 87.97 % ) " "Info: Total interconnect delay = 3.925 ns ( 87.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.462 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.462 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } { 0.000ns 2.888ns 1.037ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.459 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.459 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 2.888ns 1.034ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.462 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.462 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } { 0.000ns 2.888ns 1.037ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.821 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~758 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.821 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~758 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 1.029ns 0.756ns 0.263ns 0.243ns 0.000ns } { 0.000ns 0.420ns 0.438ns 0.438ns 0.150ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.459 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.459 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 2.888ns 1.034ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.462 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.462 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0] } { 0.000ns 2.888ns 1.037ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 register tmp_data\[15\] r