📄 prev_cmp_sram_2.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 register tmp_addr\[3\] register tmp_data\[15\] 93.585 ns " "Info: Slack time is 93.585 ns for clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" between source register \"tmp_addr\[3\]\" and destination register \"tmp_data\[15\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "155.88 MHz 6.415 ns " "Info: Fmax is 155.88 MHz (period= 6.415 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "99.775 ns + Largest register register " "Info: + Largest register to register requirement is 99.775 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "100.000 ns + " "Info: + Setup relationship between source and destination is 100.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 97.642 ns " "Info: + Latch edge is 97.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns 50 " "Info: Clock period of Source clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns + Largest " "Info: + Largest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 destination 2.628 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to destination register is 2.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 114 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 114; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.628 ns tmp_data\[15\] 3 REG LCFF_X19_Y11_N31 4 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.628 ns; Loc. = LCFF_X19_Y11_N31; Fanout = 4; REG Node = 'tmp_data\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.43 % ) " "Info: Total cell delay = 0.537 ns ( 20.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.091 ns ( 79.57 % ) " "Info: Total interconnect delay = 2.091 ns ( 79.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 source 2.639 ns - Longest register " "Info: - Longest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to source register is 2.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 114 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 114; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.537 ns) 2.639 ns tmp_addr\[3\] 3 REG LCFF_X17_Y13_N13 5 " "Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.639 ns; Loc. = LCFF_X17_Y13_N13; Fanout = 5; REG Node = 'tmp_addr\[3\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.548 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.35 % ) " "Info: Total cell delay = 0.537 ns ( 20.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.102 ns ( 79.65 % ) " "Info: Total interconnect delay = 2.102 ns ( 79.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } { 0.000ns 1.091ns 1.011ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } { 0.000ns 1.091ns 1.011ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } { 0.000ns 1.091ns 1.011ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.190 ns - Longest register register " "Info: - Longest register to register delay is 6.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp_addr\[3\] 1 REG LCFF_X17_Y13_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y13_N13; Fanout = 5; REG Node = 'tmp_addr\[3\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp_addr[3] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.420 ns) 2.059 ns LessThan1~296 2 COMB LCCOMB_X18_Y14_N28 1 " "Info: 2: + IC(1.639 ns) + CELL(0.420 ns) = 2.059 ns; Loc. = LCCOMB_X18_Y14_N28; Fanout = 1; COMB Node = 'LessThan1~296'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.059 ns" { tmp_addr[3] LessThan1~296 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 101 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.419 ns) 2.732 ns LessThan1~298 3 COMB LCCOMB_X18_Y14_N6 2 " "Info: 3: + IC(0.254 ns) + CELL(0.419 ns) = 2.732 ns; Loc. = LCCOMB_X18_Y14_N6; Fanout = 2; COMB Node = 'LessThan1~298'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { LessThan1~296 LessThan1~298 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 101 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.437 ns) 3.440 ns always0~0 4 COMB LCCOMB_X18_Y14_N30 4 " "Info: 4: + IC(0.271 ns) + CELL(0.437 ns) = 3.440 ns; Loc. = LCCOMB_X18_Y14_N30; Fanout = 4; COMB Node = 'always0~0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.708 ns" { LessThan1~298 always0~0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.414 ns) 4.614 ns tmp_data\[0\]~162 5 COMB LCCOMB_X19_Y11_N0 2 " "Info: 5: + IC(0.760 ns) + CELL(0.414 ns) = 4.614 ns; Loc. = LCCOMB_X19_Y11_N0; Fanout = 2; COMB Node = 'tmp_data\[0\]~162'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.174 ns" { always0~0 tmp_data[0]~162 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.685 ns tmp_data\[1\]~163 6 COMB LCCOMB_X19_Y11_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 4.685 ns; Loc. = LCCOMB_X19_Y11_N2; Fanout = 2; COMB Node = 'tmp_data\[1\]~163'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[0]~162 tmp_data[1]~163 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.756 ns tmp_data\[2\]~164 7 COMB LCCOMB_X19_Y11_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.756 ns; Loc. = LCCOMB_X19_Y11_N4; Fanout = 2; COMB Node = 'tmp_data\[2\]~164'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[1]~163 tmp_data[2]~164 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.827 ns tmp_data\[3\]~165 8 COMB LCCOMB_X19_Y11_N6 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.827 ns; Loc. = LCCOMB_X19_Y11_N6; Fanout = 2; COMB Node = 'tmp_data\[3\]~165'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[2]~164 tmp_data[3]~165 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.898 ns tmp_data\[4\]~166 9 COMB LCCOMB_X19_Y11_N8 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.898 ns; Loc. = LCCOMB_X19_Y11_N8; Fanout = 2; COMB Node = 'tmp_data\[4\]~166'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[3]~165 tmp_data[4]~166 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.969 ns tmp_data\[5\]~167 10 COMB LCCOMB_X19_Y11_N10 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.969 ns; Loc. = LCCOMB_X19_Y11_N10; Fanout = 2; COMB Node = 'tmp_data\[5\]~167'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[4]~166 tmp_data[5]~167 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.040 ns tmp_data\[6\]~168 11 COMB LCCOMB_X19_Y11_N12 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.040 ns; Loc. = LCCOMB_X19_Y11_N12; Fanout = 2; COMB Node = 'tmp_data\[6\]~168'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[5]~167 tmp_data[6]~168 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 5.199 ns tmp_data\[7\]~169 12 COMB LCCOMB_X19_Y11_N14 2 " "Info: 12: + IC(0.000 ns) + CELL(0.159 ns) = 5.199 ns; Loc. = LCCOMB_X19_Y11_N14; Fanout = 2; COMB Node = 'tmp_data\[7\]~169'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { tmp_data[6]~168 tmp_data[7]~169 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.270 ns tmp_data\[8\]~170 13 COMB LCCOMB_X19_Y11_N16 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.270 ns; Loc. = LCCOMB_X19_Y11_N16; Fanout = 2; COMB Node = 'tmp_data\[8\]~170'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[7]~169 tmp_data[8]~170 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.341 ns tmp_data\[9\]~171 14 COMB LCCOMB_X19_Y11_N18 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.341 ns; Loc. = LCCOMB_X19_Y11_N18; Fanout = 2; COMB Node = 'tmp_data\[9\]~171'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[8]~170 tmp_data[9]~171 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.412 ns tmp_data\[10\]~172 15 COMB LCCOMB_X19_Y11_N20 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.412 ns; Loc. = LCCOMB_X19_Y11_N20; Fanout = 2; COMB Node = 'tmp_data\[10\]~172'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[9]~171 tmp_data[10]~172 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.483 ns tmp_data\[11\]~173 16 COMB LCCOMB_X19_Y11_N22 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 5.483 ns; Loc. = LCCOMB_X19_Y11_N22; Fanout = 2; COMB Node = 'tmp_data\[11\]~173'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[10]~172 tmp_data[11]~173 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.554 ns tmp_data\[12\]~174 17 COMB LCCOMB_X19_Y11_N24 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 5.554 ns; Loc. = LCCOMB_X19_Y11_N24; Fanout = 2; COMB Node = 'tmp_data\[12\]~174'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[11]~173 tmp_data[12]~174 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.625 ns tmp_data\[13\]~175 18 COMB LCCOMB_X19_Y11_N26 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 5.625 ns; Loc. = LCCOMB_X19_Y11_N26; Fanout = 2; COMB Node = 'tmp_data\[13\]~175'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[12]~174 tmp_data[13]~175 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.696 ns tmp_data\[14\]~176 19 COMB LCCOMB_X19_Y11_N28 1 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 5.696 ns; Loc. = LCCOMB_X19_Y11_N28; Fanout = 1; COMB Node = 'tmp_data\[14\]~176'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[13]~175 tmp_data[14]~176 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 6.106 ns tmp_data\[15\]~152 20 COMB LCCOMB_X19_Y11_N30 1 " "Info: 20: + IC(0.000 ns) + CELL(0.410 ns) = 6.106 ns; Loc. = LCCOMB_X19_Y11_N30; Fanout = 1; COMB Node = 'tmp_data\[15\]~152'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { tmp_data[14]~176 tmp_data[15]~152 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.190 ns tmp_data\[15\] 21 REG LCFF_X19_Y11_N31 4 " "Info: 21: + IC(0.000 ns) + CELL(0.084 ns) = 6.190 ns; Loc. = LCFF_X19_Y11_N31; Fanout = 4; REG Node = 'tmp_data\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { tmp_data[15]~152 tmp_data[15] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 52.76 % ) " "Info: Total cell delay = 3.266 ns ( 52.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.924 ns ( 47.24 % ) " "Info: Total interconnect delay = 2.924 ns ( 47.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.190 ns" { tmp_addr[3] LessThan1~296 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.190 ns" { tmp_addr[3] LessThan1~296 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } { 0.000ns 1.639ns 0.254ns 0.271ns 0.760ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.420ns 0.419ns 0.437ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.639 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[3] } { 0.000ns 1.091ns 1.011ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.190 ns" { tmp_addr[3] LessThan1~296 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.190 ns" { tmp_addr[3] LessThan1~296 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } { 0.000ns 1.639ns 0.254ns 0.271ns 0.760ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.420ns 0.419ns 0.437ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register tmp_data\[6\] register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[80\] 484 ps " "Info: Slack time is 484 ps for clock \"CLOCK_50\" between source register \"tmp_data\[6\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[80\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.184 ns + Largest register register " "Info: + Largest register to register requirement is 2.184 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.358 ns + " "Info: + Setup relationship between source and destination is 2.358 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 17.642 ns " "Info: - Launch edge is 17.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns 50 " "Info: Clock period of Source clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.040 ns + Largest " "Info: + Largest clock skew is 0.040 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.668 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 789 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 789; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[80\] 3 REG LCFF_X18_Y13_N25 3 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X18_Y13_N25; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[80\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 source 2.628 ns - Longest register " "Info: - Longest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to source register is 2.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 114 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 114; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.628 ns tmp_data\[6\] 3 REG LCFF_X19_Y11_N13 5 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.628 ns; Loc. = LCFF_X19_Y11_N13; Fanout = 5; REG Node = 'tmp_data\[6\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.43 % ) " "Info: Total cell delay = 0.537 ns ( 20.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.091 ns ( 79.57 % ) " "Info: Total interconnect delay = 2.091 ns ( 79.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns - Longest register register " "Info: - Longest register to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp_data\[6\] 1 REG LCFF_X19_Y11_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y11_N13; Fanout = 5; REG Node = 'tmp_data\[6\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp_data[6] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.366 ns) 1.700 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[80\] 2 REG LCFF_X18_Y13_N25 3 " "Info: 2: + IC(1.334 ns) + CELL(0.366 ns) = 1.700 ns; Loc. = LCFF_X18_Y13_N25; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[80\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { tmp_data[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 21.53 % ) " "Info: Total cell delay = 0.366 ns ( 21.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 78.47 % ) " "Info: Total interconnect delay = 1.334 ns ( 78.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { tmp_data[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { tmp_data[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } { 0.000ns 1.334ns } { 0.000ns 0.366ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[6] } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { tmp_data[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { tmp_data[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[80] } { 0.000ns 1.334ns } { 0.000ns 0.366ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
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