📄 sram_2.tan.qmsg
字号:
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 register tmp_addr\[5\] register tmp_data\[15\] 93.698 ns " "Info: Slack time is 93.698 ns for clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" between source register \"tmp_addr\[5\]\" and destination register \"tmp_data\[15\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "158.68 MHz 6.302 ns " "Info: Fmax is 158.68 MHz (period= 6.302 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "99.778 ns + Largest register register " "Info: + Largest register to register requirement is 99.778 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "100.000 ns + " "Info: + Setup relationship between source and destination is 100.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 97.642 ns " "Info: + Latch edge is 97.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns 50 " "Info: Clock period of Source clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.008 ns + Largest " "Info: + Largest clock skew is -0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 destination 2.633 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to destination register is 2.633 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 114 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 114; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.537 ns) 2.633 ns tmp_data\[15\] 3 REG LCFF_X21_Y9_N31 4 " "Info: 3: + IC(1.005 ns) + CELL(0.537 ns) = 2.633 ns; Loc. = LCFF_X21_Y9_N31; Fanout = 4; REG Node = 'tmp_data\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.39 % ) " "Info: Total cell delay = 0.537 ns ( 20.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.096 ns ( 79.61 % ) " "Info: Total interconnect delay = 2.096 ns ( 79.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.005ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 source 2.641 ns - Longest register " "Info: - Longest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to source register is 2.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 114 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 114; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.537 ns) 2.641 ns tmp_addr\[5\] 3 REG LCFF_X20_Y8_N13 5 " "Info: 3: + IC(1.013 ns) + CELL(0.537 ns) = 2.641 ns; Loc. = LCFF_X20_Y8_N13; Fanout = 5; REG Node = 'tmp_addr\[5\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.550 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.33 % ) " "Info: Total cell delay = 0.537 ns ( 20.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.104 ns ( 79.67 % ) " "Info: Total interconnect delay = 2.104 ns ( 79.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } { 0.000ns 1.091ns 1.013ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.005ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } { 0.000ns 1.091ns 1.013ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.005ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } { 0.000ns 1.091ns 1.013ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.080 ns - Longest register register " "Info: - Longest register to register delay is 6.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp_addr\[5\] 1 REG LCFF_X20_Y8_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y8_N13; Fanout = 5; REG Node = 'tmp_addr\[5\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp_addr[5] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.393 ns) 1.727 ns LessThan1~297 2 COMB LCCOMB_X23_Y7_N26 1 " "Info: 2: + IC(1.334 ns) + CELL(0.393 ns) = 1.727 ns; Loc. = LCCOMB_X23_Y7_N26; Fanout = 1; COMB Node = 'LessThan1~297'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.727 ns" { tmp_addr[5] LessThan1~297 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.419 ns) 2.396 ns LessThan1~298 3 COMB LCCOMB_X23_Y7_N6 2 " "Info: 3: + IC(0.250 ns) + CELL(0.419 ns) = 2.396 ns; Loc. = LCCOMB_X23_Y7_N6; Fanout = 2; COMB Node = 'LessThan1~298'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.669 ns" { LessThan1~297 LessThan1~298 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.438 ns) 3.104 ns always0~0 4 COMB LCCOMB_X23_Y7_N10 4 " "Info: 4: + IC(0.270 ns) + CELL(0.438 ns) = 3.104 ns; Loc. = LCCOMB_X23_Y7_N10; Fanout = 4; COMB Node = 'always0~0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.708 ns" { LessThan1~298 always0~0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.414 ns) 4.504 ns tmp_data\[0\]~162 5 COMB LCCOMB_X21_Y9_N0 2 " "Info: 5: + IC(0.986 ns) + CELL(0.414 ns) = 4.504 ns; Loc. = LCCOMB_X21_Y9_N0; Fanout = 2; COMB Node = 'tmp_data\[0\]~162'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { always0~0 tmp_data[0]~162 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.575 ns tmp_data\[1\]~163 6 COMB LCCOMB_X21_Y9_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 4.575 ns; Loc. = LCCOMB_X21_Y9_N2; Fanout = 2; COMB Node = 'tmp_data\[1\]~163'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[0]~162 tmp_data[1]~163 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.646 ns tmp_data\[2\]~164 7 COMB LCCOMB_X21_Y9_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.646 ns; Loc. = LCCOMB_X21_Y9_N4; Fanout = 2; COMB Node = 'tmp_data\[2\]~164'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[1]~163 tmp_data[2]~164 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.717 ns tmp_data\[3\]~165 8 COMB LCCOMB_X21_Y9_N6 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.717 ns; Loc. = LCCOMB_X21_Y9_N6; Fanout = 2; COMB Node = 'tmp_data\[3\]~165'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[2]~164 tmp_data[3]~165 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.788 ns tmp_data\[4\]~166 9 COMB LCCOMB_X21_Y9_N8 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.788 ns; Loc. = LCCOMB_X21_Y9_N8; Fanout = 2; COMB Node = 'tmp_data\[4\]~166'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[3]~165 tmp_data[4]~166 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.859 ns tmp_data\[5\]~167 10 COMB LCCOMB_X21_Y9_N10 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.859 ns; Loc. = LCCOMB_X21_Y9_N10; Fanout = 2; COMB Node = 'tmp_data\[5\]~167'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[4]~166 tmp_data[5]~167 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.930 ns tmp_data\[6\]~168 11 COMB LCCOMB_X21_Y9_N12 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.930 ns; Loc. = LCCOMB_X21_Y9_N12; Fanout = 2; COMB Node = 'tmp_data\[6\]~168'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[5]~167 tmp_data[6]~168 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 5.089 ns tmp_data\[7\]~169 12 COMB LCCOMB_X21_Y9_N14 2 " "Info: 12: + IC(0.000 ns) + CELL(0.159 ns) = 5.089 ns; Loc. = LCCOMB_X21_Y9_N14; Fanout = 2; COMB Node = 'tmp_data\[7\]~169'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { tmp_data[6]~168 tmp_data[7]~169 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.160 ns tmp_data\[8\]~170 13 COMB LCCOMB_X21_Y9_N16 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.160 ns; Loc. = LCCOMB_X21_Y9_N16; Fanout = 2; COMB Node = 'tmp_data\[8\]~170'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[7]~169 tmp_data[8]~170 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.231 ns tmp_data\[9\]~171 14 COMB LCCOMB_X21_Y9_N18 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.231 ns; Loc. = LCCOMB_X21_Y9_N18; Fanout = 2; COMB Node = 'tmp_data\[9\]~171'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[8]~170 tmp_data[9]~171 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.302 ns tmp_data\[10\]~172 15 COMB LCCOMB_X21_Y9_N20 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.302 ns; Loc. = LCCOMB_X21_Y9_N20; Fanout = 2; COMB Node = 'tmp_data\[10\]~172'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[9]~171 tmp_data[10]~172 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.373 ns tmp_data\[11\]~173 16 COMB LCCOMB_X21_Y9_N22 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 5.373 ns; Loc. = LCCOMB_X21_Y9_N22; Fanout = 2; COMB Node = 'tmp_data\[11\]~173'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[10]~172 tmp_data[11]~173 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.444 ns tmp_data\[12\]~174 17 COMB LCCOMB_X21_Y9_N24 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 5.444 ns; Loc. = LCCOMB_X21_Y9_N24; Fanout = 2; COMB Node = 'tmp_data\[12\]~174'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[11]~173 tmp_data[12]~174 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.515 ns tmp_data\[13\]~175 18 COMB LCCOMB_X21_Y9_N26 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 5.515 ns; Loc. = LCCOMB_X21_Y9_N26; Fanout = 2; COMB Node = 'tmp_data\[13\]~175'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[12]~174 tmp_data[13]~175 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.586 ns tmp_data\[14\]~176 19 COMB LCCOMB_X21_Y9_N28 1 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 5.586 ns; Loc. = LCCOMB_X21_Y9_N28; Fanout = 1; COMB Node = 'tmp_data\[14\]~176'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_data[13]~175 tmp_data[14]~176 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.996 ns tmp_data\[15\]~152 20 COMB LCCOMB_X21_Y9_N30 1 " "Info: 20: + IC(0.000 ns) + CELL(0.410 ns) = 5.996 ns; Loc. = LCCOMB_X21_Y9_N30; Fanout = 1; COMB Node = 'tmp_data\[15\]~152'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { tmp_data[14]~176 tmp_data[15]~152 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.080 ns tmp_data\[15\] 21 REG LCFF_X21_Y9_N31 4 " "Info: 21: + IC(0.000 ns) + CELL(0.084 ns) = 6.080 ns; Loc. = LCFF_X21_Y9_N31; Fanout = 4; REG Node = 'tmp_data\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { tmp_data[15]~152 tmp_data[15] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.240 ns ( 53.29 % ) " "Info: Total cell delay = 3.240 ns ( 53.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.840 ns ( 46.71 % ) " "Info: Total interconnect delay = 2.840 ns ( 46.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.080 ns" { tmp_addr[5] LessThan1~297 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.080 ns" { tmp_addr[5] LessThan1~297 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } { 0.000ns 1.334ns 0.250ns 0.270ns 0.986ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.419ns 0.438ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.633 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_data[15] } { 0.000ns 1.091ns 1.005ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.641 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[5] } { 0.000ns 1.091ns 1.013ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.080 ns" { tmp_addr[5] LessThan1~297 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.080 ns" { tmp_addr[5] LessThan1~297 LessThan1~298 always0~0 tmp_data[0]~162 tmp_data[1]~163 tmp_data[2]~164 tmp_data[3]~165 tmp_data[4]~166 tmp_data[5]~167 tmp_data[6]~168 tmp_data[7]~169 tmp_data[8]~170 tmp_data[9]~171 tmp_data[10]~172 tmp_data[11]~173 tmp_data[12]~174 tmp_data[13]~175 tmp_data[14]~176 tmp_data[15]~152 tmp_data[15] } { 0.000ns 1.334ns 0.250ns 0.270ns 0.986ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.419ns 0.438ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register data_out\[8\]~reg0 register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[48\] 483 ps " "Info: Slack time is 483 ps for clock \"CLOCK_50\" between source register \"data_out\[8\]~reg0\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[48\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.171 ns + Largest register register " "Info: + Largest register to register requirement is 2.171 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.358 ns + " "Info: + Setup relationship between source and destination is 2.358 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 17.642 ns " "Info: - Launch edge is 17.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns 50 " "Info: Clock period of Source clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.027 ns + Largest " "Info: + Largest clock skew is 0.027 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.693 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 1658 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 1658; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.693 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[48\] 3 REG LCFF_X29_Y6_N31 3 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.693 ns; Loc. = LCFF_X29_Y6_N31; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[48\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.04 % ) " "Info: Total cell delay = 1.536 ns ( 57.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 42.96 % ) " "Info: Total interconnect delay = 1.157 ns ( 42.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 source 2.666 ns - Longest register " "Info: - Longest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to source register is 2.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 114 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 114; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.537 ns) 2.666 ns data_out\[8\]~reg0 3 REG LCFF_X29_Y6_N23 2 " "Info: 3: + IC(1.038 ns) + CELL(0.537 ns) = 2.666 ns; Loc. = LCFF_X29_Y6_N23; Fanout = 2; REG Node = 'data_out\[8\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.14 % ) " "Info: Total cell delay = 0.537 ns ( 20.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.129 ns ( 79.86 % ) " "Info: Total interconnect delay = 2.129 ns ( 79.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.688 ns - Longest register register " "Info: - Longest register to register delay is 1.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_out\[8\]~reg0 1 REG LCFF_X29_Y6_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y6_N23; Fanout = 2; REG Node = 'data_out\[8\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_out[8]~reg0 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 66 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.366 ns) 1.688 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[48\] 2 REG LCFF_X29_Y6_N31 3 " "Info: 2: + IC(1.322 ns) + CELL(0.366 ns) = 1.688 ns; Loc. = LCFF_X29_Y6_N31; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[48\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.688 ns" { data_out[8]~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 21.68 % ) " "Info: Total cell delay = 0.366 ns ( 21.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 78.32 % ) " "Info: Total interconnect delay = 1.322 ns ( 78.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.688 ns" { data_out[8]~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.688 ns" { data_out[8]~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } { 0.000ns 1.322ns } { 0.000ns 0.366ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl data_out[8]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.688 ns" { data_out[8]~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.688 ns" { data_out[8]~reg0 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48] } { 0.000ns 1.322ns } { 0.000ns 0.366ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
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