prev_cmp_sram_2.qmsg

8x8DCT verilog code 一次輸入8個點

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 30 14:45:21 2008 " "Info: Processing started: Fri May 30 14:45:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SRAM_2 -c SRAM_2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SRAM_2 -c SRAM_2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK_10MHZ.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CLK_10MHZ.v" { { "Info" "ISGN_ENTITY_NAME" "1 CLK_10MHZ " "Info: Found entity 1: CLK_10MHZ" {  } { { "CLK_10MHZ.v" "" { Text "D:/41/SRAM_2/CLK_10MHZ.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "SRAM_2.v(86) " "Warning (10273): Verilog HDL warning at SRAM_2.v(86): extended using \"x\" or \"z\"" {  } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 86 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAM_2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAM_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAM_2 " "Info: Found entity 1: SRAM_2" {  } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SRAM_2 " "Info: Elaborating entity \"SRAM_2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 SRAM_2.v(49) " "Warning (10230): Verilog HDL assignment warning at SRAM_2.v(49): truncated value with size 32 to match size of target (1)" {  } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 SRAM_2.v(52) " "Warning (10230): Verilog HDL assignment warning at SRAM_2.v(52): truncated value with size 32 to match size of target (1)" {  } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 SRAM_2.v(74) " "Warning (10230): Verilog HDL assignment warning at SRAM_2.v(74): truncated value with size 32 to match size of target (16)" {  } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 SRAM_2.v(86) " "Warning (10230): Verilog HDL assignment warning at SRAM_2.v(86): truncated value with size 32 to match size of target (16)" {  } { { "SRAM_2.v" "" { Text "D:/41/SRAM_2/SRAM_2.v" 86 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}