sram_2.tan.summary

8x8DCT verilog code 一次輸入8個點

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.253 ns
From           : KEY[0]
To             : tmp_data[15]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.561 ns
From           : HEX1[3]~reg0
To             : HEX1[3]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.613 ns
From           : KEY[0]
To             : SRAM_WE_N
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.801 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 0.483 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : data_out[8]~reg0
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48]
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'
Slack          : 93.698 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : 158.68 MHz ( period = 6.302 ns )
From           : tmp_addr[5]
To             : tmp_data[15]
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLK_10MHZ:M1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 94.75 MHz ( period = 10.554 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Hold: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'
Slack          : 0.531 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : tmp_data[15]
To             : tmp_data[15]
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLK_10MHZ:M1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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