sram_2.tan.rpt

8x8DCT verilog code 一次輸入8個點

; Worst-case th                                             ; N/A       ; None                              ; 2.801 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                                                                               ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]                                                                                                                    ; --                                         ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Setup: 'CLOCK_50'                                   ; 0.483 ns  ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; data_out[8]~reg0                                                                                                                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[48]                                                                                                ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLOCK_50                                   ; 0            ;
; Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0' ; 93.698 ns ; 10.00 MHz ( period = 100.000 ns ) ; 158.68 MHz ( period = 6.302 ns ) ; tmp_addr[5]                                                                                                                                                                                ; tmp_data[15]                                                                                                                                                                               ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'               ; N/A       ; None                              ; 94.75 MHz ( period = 10.554 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]                                                                                                                                         ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                                                           ; altera_internal_jtag~TCKUTAP               ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Hold: 'CLOCK_50'                                    ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; CLOCK_50                                   ; CLOCK_50                                   ; 0            ;
; Clock Hold: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'  ; 0.531 ns  ; 10.00 MHz ( period = 100.000 ns ) ; N/A                              ; tmp_data[15]                                                                                                                                                                               ; tmp_data[15]                                                                                                                                                                               ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                              ;           ;                                   ;                                  ;                                                                                                                                                                                            ;                                                                                                                                                                                            ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+-----------+-----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 10.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 1                     ; 5                   ; -2.358 ns ;              ;
; CLOCK_50                                   ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP               ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From         ; To                 ; From Clock                                 ; To Clock                                   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 93.698 ns                               ; 158.68 MHz ( period = 6.302 ns )                    ; tmp_addr[5]  ; tmp_data[15]       ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.778 ns                 ; 6.080 ns                ;