📄 sram2.stp

📁 8x8DCT verilog code 一次輸入8個點
💻 STP
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<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C35 (0x020B40DD)" sof_file="SRAM_2.sof" top_level_entity="SRAM_2">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance compilation_mode="full" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="5"/>
    <position_info>
      <single attribute="active tab" value="1"/>
      <single attribute="data horizontal scroll position" value="0"/>
      <single attribute="data vertical scroll position" value="0"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom level numerator" value="1"/>
      <single attribute="zoom offset denominator" value="1"/>
      <single attribute="zoom offset numerator" value="130048"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2008/06/02 16:32:13  #0">
      <clock name="CLOCK_50" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="SRAM_ADDR[0]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[10]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[11]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[12]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[13]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[14]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[15]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[16]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[17]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[1]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[2]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[3]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[4]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[5]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[6]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[7]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[8]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[9]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_DQ[0]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[10]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[11]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[12]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[13]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[14]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[15]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[1]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[2]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[3]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[4]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[5]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[6]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[7]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[8]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[9]" tap_mode="classic" type="bidir pin"/>
          <wire name="data_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="tmp_addr[0]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[10]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[11]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[12]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[13]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[14]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[15]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[16]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[17]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[1]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[2]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[3]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[4]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[5]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[6]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[7]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[8]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[9]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[0]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[10]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[11]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[12]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[13]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[14]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[15]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[1]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[2]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[3]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[4]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[5]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[6]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[7]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[8]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[9]" tap_mode="classic" type="register"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="SRAM_ADDR[0]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[10]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[11]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[12]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[13]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[14]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[15]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[16]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[17]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[1]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[2]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[3]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[4]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[5]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[6]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[7]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[8]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_ADDR[9]" tap_mode="classic" type="output pin"/>
          <wire name="SRAM_DQ[0]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[10]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[11]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[12]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[13]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[14]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[15]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[1]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[2]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[3]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[4]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[5]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[6]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[7]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[8]" tap_mode="classic" type="bidir pin"/>
          <wire name="SRAM_DQ[9]" tap_mode="classic" type="bidir pin"/>
          <wire name="data_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="data_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="tmp_addr[0]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[10]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[11]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[12]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[13]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[14]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[15]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[16]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[17]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[1]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[2]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[3]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[4]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[5]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[6]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[7]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[8]" tap_mode="classic" type="register"/>
          <wire name="tmp_addr[9]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[0]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[10]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[11]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[12]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[13]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[14]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[15]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[1]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[2]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[3]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[4]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[5]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[6]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[7]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[8]" tap_mode="classic" type="register"/>
          <wire name="tmp_data[9]" tap_mode="classic" type="register"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="tmp_data" order="lsb_to_msb" radix="hex" state="collapse" type="register">
            <net is_signal_inverted="no" name="tmp_data[0]"/>
            <net is_signal_inverted="no" name="tmp_data[1]"/>
            <net is_signal_inverted="no" name="tmp_data[2]"/>
            <net is_signal_inverted="no" name="tmp_data[3]"/>
            <net is_signal_inverted="no" name="tmp_data[4]"/>
            <net is_signal_inverted="no" name="tmp_data[5]"/>
            <net is_signal_inverted="no" name="tmp_data[6]"/>
            <net is_signal_inverted="no" name="tmp_data[7]"/>
12 下一页
💿 文件大小 8220 K
👤 上传用户 yamiluoier
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#verilog #8x8DCT #code
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