dct.v

8x8DCT verilog code 一次輸入8個點

module DCT(
	iclk,
	d0,d1,d2,d3,d4,d5,d6,d7,
	inpull,
	m0,m1,m2,m3,m4,m5,m6,m7,
	c1,c0,work1,work2,outpull,
	F0_S,F1_S,F2_S,F3_S,F4_S,F5_S,F6_S,F7_S
	);

input [7:0] d0,d1,d2,d3,d4,d5,d6,d7;
input inpull,iclk;

output [16:0] m0,m1,m2,m3,m4,m5,m6,m7;
output [2:0]c1,c0;
output work1,work2,outpull;
output [12:0]F0_S,F1_S,F2_S,F3_S,F4_S,F5_S,F6_S,F7_S;

reg [12:0]F[7:0][7:0];
reg [2:0]c0,c1;
reg work1,work2;

reg [12:0] F0_r,F1_r,F2_r,F3_r,F4_r,F5_r,F6_r,F7_r;
reg outpull;

//wire [16:0] m0_r,m1_r,m2_r,m3_r,m4_r,m5_r,m6_r,m7_r;

wire [16:0]m0,m1,m2,m3,m4,m5,m6,m7;
wire [12:0] F0_w,F1_w,F2_w,F3_w,F4_w,F5_w,F6_w,F7_w;
wire [12:0]F0_S,F1_S,F2_S,F3_S,F4_S,F5_S,F6_S,F7_S;

wire [12:0]F0,F1,F2,F3,F4,F5,F6,F7;

DCT_1d_8b DCT_1d_8b(F0,F1,F2,F3,F4,F5,F6,F7,d0,d1,d2,d3,d4,d5,d6,d7);
DCT_1d_13bS DCT_1d_13bS(m0,m1,m2,m3,m4,m5,m6,m7,F0_r,F1_r,F2_r,F3_r,F4_r,F5_r,F6_r,F7_r);

assign F0_S = (work1 == 1'b1)?F0:0;
assign F1_S = (work1 == 1'b1)?F1:0;
assign F2_S = (work1 == 1'b1)?F2:0;
assign F3_S = (work1 == 1'b1)?F3:0;
assign F4_S = (work1 == 1'b1)?F4:0;
assign F5_S = (work1 == 1'b1)?F5:0;
assign F6_S = (work1 == 1'b1)?F6:0;
assign F7_S = (work1 == 1'b1)?F7:0;

//assign m0 = m0_r[8:1];
//assign m1 = m1_r[8:1];
//assign m2 = m2_r[8:1];
//assign m3 = m3_r[8:1];
//assign m4 = m4_r[8:1];
//assign m5 = m5_r[8:1];
//assign m6 = m6_r[8:1];
//assign m7 = m7_r[8:1];

always@ (posedge iclk)
begin
	if (inpull == 1'b1)
	begin
		c0 = 3'b000;
		work1 = 1'b1;
		outpull = 1'b0;
		work2 = 1'b0;
	end
	
	if (work2 == 1'b1)
	begin
	case (c1)
		3'b000:
		begin
			F0_r = F[0][0];
			F1_r = F[1][0];
			F2_r = F[2][0];
			F3_r = F[3][0];
			F4_r = F[4][0];
			F5_r = F[5][0];
			F6_r = F[6][0];
			F7_r = F[7][0];
		end
		3'b001:
		begin
			F0_r = F[0][1];
			F1_r = F[1][1];
			F2_r = F[2][1];
			F3_r = F[3][1];
			F4_r = F[4][1];
			F5_r = F[5][1];
			F6_r = F[6][1];
			F7_r = F[7][1];
		end
		3'b010:
		begin
			F0_r = F[0][2];
			F1_r = F[1][2];
			F2_r = F[2][2];
			F3_r = F[3][2];
			F4_r = F[4][2];
			F5_r = F[5][2];
			F6_r = F[6][2];
			F7_r = F[7][2];
		end
		3'b011:
		begin
			F0_r = F[0][3];
			F1_r = F[1][3];
			F2_r = F[2][3];
			F3_r = F[3][3];
			F4_r = F[4][3];
			F5_r = F[5][3];
			F6_r = F[6][3];
			F7_r = F[7][3];
		end
		3'b100:
		begin
			F0_r = F[0][4];
			F1_r = F[1][4];
			F2_r = F[2][4];
			F3_r = F[3][4];
			F4_r = F[4][4];
			F5_r = F[5][4];
			F6_r = F[6][4];
			F7_r = F[7][4];
		end
		3'b101:
		begin
			F0_r = F[0][5];
			F1_r = F[1][5];
			F2_r = F[2][5];
			F3_r = F[3][5];
			F4_r = F[4][5];
			F5_r = F[5][5];
			F6_r = F[6][5];
			F7_r = F[7][5];
		end
		3'b110:
		begin
			F0_r = F[0][6];
			F1_r = F[1][6];
			F2_r = F[2][6];
			F3_r = F[3][6];
			F4_r = F[4][6];
			F5_r = F[5][6];
			F6_r = F[6][6];
			F7_r = F[7][6];
		end
		3'b111:
		begin
			F0_r = F[0][7];
			F1_r = F[1][7];
			F2_r = F[2][7];
			F3_r = F[3][7];
			F4_r = F[4][7];
			F5_r = F[5][7];
			F6_r = F[6][7];
			F7_r = F[7][7];
		end
	endcase
	work2 = (c1 == 3'b111)?1'b0:1'b1;
	outpull = (work2 == 1'b0)?1'b1:1'b0;
	c1 = c1 + 1'b1;	
	end
		
	if (work1 == 1'b1)
	begin 
	case (c0)
		3'b000:
		begin
			F[0][0] = F0;
			F[0][1] = F1;
			F[0][2] = F2;
			F[0][3] = F3;
			F[0][4] = F4;
			F[0][5] = F5;
			F[0][6] = F6;
			F[0][7] = F7;
		end	
		3'b001:
		begin
			F[1][0] = F0;
			F[1][1] = F1;
			F[1][2] = F2;
			F[1][3] = F3;
			F[1][4] = F4;
			F[1][5] = F5;
			F[1][6] = F6;
			F[1][7] = F7;
		end	
		3'b010:
		begin
			F[2][0] = F0;
			F[2][1] = F1;
			F[2][2] = F2;
			F[2][3] = F3;
			F[2][4] = F4;
			F[2][5] = F5;
			F[2][6] = F6;
			F[2][7] = F7;
		end	
		3'b011:
		begin
			F[3][0] = F0;
			F[3][1] = F1;
			F[3][2] = F2;
			F[3][3] = F3;
			F[3][4] = F4;
			F[3][5] = F5;
			F[3][6] = F6;
			F[3][7] = F7;
		end	
		3'b100:
		begin
			F[4][0] = F0;
			F[4][1] = F1;
			F[4][2] = F2;
			F[4][3] = F3;
			F[4][4] = F4;
			F[4][5] = F5;
			F[4][6] = F6;
			F[4][7] = F7;
		end	
		3'b101:
		begin
			F[5][0] = F0;
			F[5][1] = F1;
			F[5][2] = F2;
			F[5][3] = F3;
			F[5][4] = F4;
			F[5][5] = F5;
			F[5][6] = F6;
			F[5][7] = F7;
		end	
		3'b110:
		begin
			F[6][0] = F0;
			F[6][1] = F1;
			F[6][2] = F2;
			F[6][3] = F3;
			F[6][4] = F4;
			F[6][5] = F5;
			F[6][6] = F6;
			F[6][7] = F7;
		end	
		3'b111:
		begin
			F[7][0] = F0;
			F[7][1] = F1;
			F[7][2] = F2;
			F[7][3] = F3;
			F[7][4] = F4;
			F[7][5] = F5;
			F[7][6] = F6;
			F[7][7] = F7;
		end	
	endcase
	work1 = (c0 == 3'b111)?1'b0:1'b1;
	work2 = (work1 == 1'b0)?1'b1:1'b0;
	c1 = 3'b000;
	c0 = c0 + 1'b1;
	end
end
endmodule